AK4671_10 Datasheet, PDF (148/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
2. PLL Slave Mode (MCKI pin)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D0)
MCKO bit
(Addr:02H, D2)
PMPLL bit
(Addr:02H, D0)
MCKI pin
MCKO pin
BICK pin
LRCK pin
(1)
(2) (3)
(4)
(5)
Input
40m s ec(m ax)
(7)
(6)
(8)
Output
Input
Example:
Audio I/F Format: MSB justified (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
(2)Addr:03H, Data:02H
Addr:01H, Data:F4H
(3)Addr:00H, Data:01H
(4)Addr:02H, Data:25H
MCKO output start
BICK and LRCK input start
Figure 110. Clock Set Up Sequence (2)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max.).
(6) The normal clock is output from MCKO during this period.
(7) The invalid frequency is output from MCKO after PLL is locked.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
MS0666-E-02
- 148 -
2010/06