AK4671_10 Datasheet, PDF (149/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
3. PLL Slave Mode (LRCK or BICK pin)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D0)
PMPLL bit
(Addr:02H, D0)
LRCK pin
BICK pin
Internal Clock
(1)
(2) (3)
Example:
Audio I/F Format : MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
4f₍s₁o₎ f_{Power Supply & PDN pin = “L” Æ “H”}
Input
(4)
(2) Addr:03H, Data:02H
Addr:01H, Data:83H
(3) Addr:00H, Data:01H
(5)
(4) Addr:02H, Data:01H
Figure 111. Clock Set Up Sequence (3)
<Example>
(1) After Power Up, PDN pin = “L” Æ “H”. “L” time of 150ns or more is needed to reset the AK4671.
The AK4671 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid pop noise at the receiver output, headphone output and
lineout output.
(2) DIF1-0, FS3-2 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
supplied. PLL lock time is 160ms(max.) when LRCK is a PLL reference clock. And PLL lock time is
2ms(max.) when BICK is a PLL reference clock.
(5) Normal operation stats after that the PLL is locked.
MS0666-E-02
- 149 -
2010/06