AK4671_10 Datasheet, PDF (5/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
No. Pin Name
I/O
Function
J8 SDTIA
I Serial Data Input A Pin
G8 BICKA
I/O Serial Data Clock A Pin
H9 SYNCA
I/O Sync Signal A Pin
G9 SDTOA
O Serial Data Output A Pin
F8 TVDD2
- Digital I/O Power Supply 2 Pin, 1.6 ∼ 3.6V
F9 VSS2
- Ground 2 Pin
E8 PVDD
- PLLBT Power Supply Pin, 2.2 ∼ 3.6V
E9 VCOCBT
O
Output Pin for Loop Filter of PLLBT Circuit
This pin should be connected to VSS2 pin with one resistor and capacitor in series.
D8 VCOC
O
Output Pin for Loop Filter of PLL Circuit
This pin should be connected to VSS1 pin with one resistor and capacitor in series.
D9 VCOM
O
Common Voltage Output Pin, 0.5 x AVDD
Bias voltage of ADC inputs and DAC outputs.
C8 MUTET
O
Mute Time Constant Control Pin
Connected to VSS1 pin with a capacitor for mute time constant.
C9 ROUT2
O Rch Headphone-Amp Output Pin
B9 LOUT2
O Lch Headphone-Amp Output Pin
A9 TEST
-
Test Pin
This pin should be open.
A8 AVDD
- Analog Power Supply Pin, 2.2 ∼ 3.6V
B8 VSS1
- Ground 1 Pin
B7 ^ROUT1
RCN
O Rch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
O Receiver-Amp Negative Output Pin (RCV bit = “1”: Receiver Output)
A7 ^LOUT1
RCP
O Lch Stereo Line Output 1 Pin (RCV bit = “0”: Stereo Line Output)
O Receiver-Amp Positive Output Pin (RCV bit = “1”: Receiver Output)
A6
ROUT3
LON
O Rch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
O Negative Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
B6
LOUT3
LOP
O Lch Stereo Line Output 3 Pin (LODIF bit = “0”: Single-ended Stereo Output)
O Positive Line Output Pin (LODIF bit = “1”: Full-differential Mono Output)
A5
RIN4
IN4−
I Rch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
I Negative Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
B5 ^LIN4
IN4+
I Lch Analog Input 4 Pin (MDIF4 bit = “0”: Single-ended Input)
I Positive Line Input 4 Pin (MDIF4 bit = “1”: Full-differential Input)
B4
RIN3
IN3−
I Rch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
I Negative Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
A4
LIN3
IN3+
I Lch Analog Input 3 Pin (MDIF3 bit = “0”: Single-ended Input)
I Positive Line Input 3 Pin (MDIF3 bit = “1”: Full-differential Input)
B3
RIN2
IN2−
I Rch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
I Negative Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
A3 ^LIN2
IN2+
I Lch Analog Input 2 Pin (MDIF2 bit = “0”: Single-ended Input)
I Positive Line Input 2 Pin (MDIF2 bit = “1”: Full-differential Input)
B2
RIN1
IN1−
I Rch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
I Negative Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
A2
LIN1
IN1+
I Lch Analog Input 1 Pin (MDIF1 bit = “0”: Single-ended Input)
I Positive Line Input 1 Pin (MDIF1 bit = “1”: Full-differential Input)
C3 NC
-
No Connect Pin
No internal bonding. This pin should be open or connected to the ground.
Note 1. All input pins except analog input pins (MDT, LIN1/IN1+, RIN1/IN1−, LIN2/IN2+, RIN2/IN2−, LIN3/IN3+,
RIN3/IN3−, LIN4/IN4+, RIN4/IN4−, SAIN1, SAIN2, SAIN3) should not be left floating.
I/O pins except SDA pin (LRCK, BICK, SYNCA, BICKA, SYNCB, BICKB) should be processed appropriately.
Please refer the “Master Mode/Slave Mode” (P.45) and “PCM I/F Master Mode/Slave Mode” (P.105). SDA pin
should be pulled-up by a resistor externally and be connected to (DVDD+0.3)V or less voltage.
MS0666-E-02
-5-
2010/06