AK4671_10 Datasheet, PDF (25/166 Pages) Asahi Kasei Microsystems – Stereo CODEC with MIC/RCV/HP-AMP

[AK4671]
Parameter
Symbol
min
Control Interface Timing (4-wire Serial mode)
CCLK Period (Note 51)
tCCK
200
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
80
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
40
CSN “H” Time
tCSW
150
CSN Edge to CCLK “↑” (Note 52)
tCSS
50
CCLK “↑” to CSN Edge (Note 52)
tCSH
50
CDTO Delay
tDCD
-
CSN “↑” to CDTO Hi-Z
tCCZ
-
Control Interface Timing (I²C Bus mode): (Note 50)
SCL Clock Frequency (Note 53)
Bus Free Time Between Transmissions
fSCL
30
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA
0.6
SDA Hold Time from SCL Falling (Note 54)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Capacitive Load on Bus
Cb
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Power-down & Reset Timing
PDN Pulse Width (Note 55)
tPD
150
PMADL or PMADR “↑” to SDTO valid (Note 56)
tPDV
-
PMSRA “↑” to SDTOA valid (Note 57)
tPDV2
-
PMSRB “↑” to SDTO valid (Note 58)
tPDV3
-
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1059
21
135
max
33000
-
-
-
-
-
-
-
70
70
400
-
-
-
-
-
-
-
0.3
0.3
-
400
50
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
ns
1/fs
1/fs2
1/fs
Note 50. I²C-bus is a trademark of NXP B.V.
Note 51. CCLK should be input succeedingly until 10bit data of SAR ADC is read out at 4-wire serial mode (Figure 97).
Note 52. CCLK rising edge must not occur at the same time as CSN edge.
Note 53. In case that SAR ADC data is read out via I²C bus, SCL should be input succeedingly corresponding 2 byte data
including ACK (Figure 104).
Note 54. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 55. The AK4671 can be reset by bringing PDN pin = “L” to “H” only upon power up.
Note 56. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1” at PMSRB bit = “1”.
Note 57. The signal path is SDTI → SRC-A → SDTOA and PLLBT is locked.
Note 58. The signal path is SDTIA → SRC-B → SDTO.
MS0666-E-02
- 25 -
2010/06