Z8S18020VSG Datasheet, PDF (68/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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+1 %10641. 4')+56'4
The I/O Control Register (+%4) allows relocation of the in-
ternal I/O addresses. +%4 also controls the enabling and dis-
abling of +15612 mode (Figure 83).
$KV 







+1# +1# +1562
49 49 49
(KIWTG  +1 %QPVTQN 4GIKUVGT +%4 +1 #FFTGUU  (*
ZiLOG
+1#  +1 #FFTGUU 4GNQECVKQP $KVU  + 1 #  a n d
+1# relocate internal I/O as indicated in Figure 84.
0QVG The high-order 8 bits of 16-bit internal I/O address are al-
ways 0. +1# and +1# are cleared to 0 during 4'5'6.
+1# +1#   
+1# +1#   
+1# +1#   
+1# +1#   
((*
%*
$(*
*
(*
*
(*
*
(KIWTG  +1 #FFTGUU 4GNQECVKQP
+1562 +15612 /QFG $KV  +15612 mode is enabled
when +1562 is set to 1. Normal I/O operation resumes when
+1562 is reprogrammed or 4'5'6 to 0.

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