Z8S18020VSG Datasheet, PDF (46/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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'PJCPEGF < /KETQRTQEGUUQT
ZiLOG
#5%+ 4'%'+8' 4')+56'4
Register addresses 08H and 09H hold the ASCI receive data
for channel 0 and channel 1, respectively.
#5%+ 4GEGKXG 4GIKUVGT %JCPPGN 
#5%+ 4GEGKXG 4GIKUVGT %JCPPGN 
/PGOQPKE 4&4
#FFTGUU *
/PGOQPKE 4&4
#FFTGUU *
     
     
#5%+ 6TCPUOKV &CVC
(KIWTG  #5%+ 4GEGKXG 4GIKUVGT %JCPPGN 
#5%+ 6TCPUOKV &CVC
(KIWTG  #5%+ 4GEGKXG 4GIKUVGT %JCPPGN 
%5+1 %10641.56#675 4')+56'4
The CSI/O Control/Status Register (%064) is used to mon-
itor CSI/O status, enable and disable the CSI/O, enable and
disable interrupt generation, and select the data clock speed
and source.
$KV








'(
'+'
4'
6'
AA
55
55
55
4
49
49
49
49
49
49
(KIWTG  %5+1 %QPVTQN 4GIKUVGT %064 +1 #FFTGUU  #*
'( 'PF (NCI $KV  '( is set to 1 by the CSI/O to indicate
completion of an 8-bit data transmit or receive operation.
If End Interrupt Enable ('+') bit = 1 when '( is set to 1,
a CPU interrupt request is generated. Program access of
64&4 only occurs if '(  1. The CSI/O clears '( to 0 when
64&4 is read or written. '( is cleared to 0 during 4'5'6
and +15612 mode.
'+' 'PF +PVGTTWRV 'PCDNG $KV  '+' is set to 1 to gen-
erate a CPU interrupt request. The interrupt request is in-
hibited if '+' is reset to 0. '+' is cleared to 0 during 4'5'6.
4' 4GEGKXG 'PCDNG $KV  A CSI/O receive operation is
started by setting 4' to 1. When 4' is set to 1, the data clock
is enabled. In internal clock mode, the data clock is output
from the %-5 pin. In external clock mode, the clock is input
on the %-5 pin. In either case, data is shifted in on the 4:5
pin in synchronization with the (internal or external) data
clock. After receiving 8 bits of data, the CSI/O automati-
cally clears 4' to 0, '( is set to 1, and an interrupt (if enabled
by '+'  ) is generated. 4' and 6' are never both set to
1 at the same time. 4' is cleared to 0 during 4'5'6 and
+15612 mode.
6' 6TCPUOKV 'PCDNG $KV  A CSI/O transmit operation
is started by setting 6' to 1. When 6' is set to 1, the data
clock is enabled. When in internal clock mode, the data
clock is output from the %-5 pin. In external clock mode,
the clock is input on the %-5 pin. In either case, data is shift-
ed out on the 6:5 pin synchronous with the (internal or ex-
ternal) data clock. After transmitting 8 bits of data, the
CSI/O automatically clears 6' to 0, sets '( to 1, and re-
quests an interrupt if enabled by '+'  1. 6' and 4' are

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