Z8S18020VSG Datasheet, PDF (39/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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$KV  .0+1 This bit controls the drive capability of certain
external I/O pins of the Z8S180/Z8L180. When this bit is
set to 1, the output drive capability of the following pins is
reduced to 33 percent of the original drive capability:
$KV  .0%27%6. This bit controls the drive capability of
the CPU Control pins. When this bit is set to 1, the output
drive capability of the following pins is reduced to 33 per-
cent of the original drive capability:
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$KV  .0#&&#6# This bit controls the drive capability of
the Address/Data bus output drivers. If this bit is set to 1,
the output drive capability of the Address and Data bus out-
puts is reduced to 33 percent of its original drive capability.
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