Z8S18020VSG Datasheet, PDF (51/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
<5<.
'PJCPEGF < /KETQRTQEGUUQT
#5%+ 6+/' %1056#06 4')+56'45
If the 55  bits of the %06.$ register are not , and
the $4) mode bit in the #5':6 register is 1, the #5%+ di-
vides the 2*+ clock by two times the registers’ 16-bit value,
plus two. As a result, the clock is presented to the transmitter
and receiver for division by 1, 16, or 64, and is output on
the %-# pin.
If the 55  bits in an ASCI %06.$ register are not 111,
and the $4) mode bit in its Extension Control Register is
1, its new baud rate generator divides 2*+ for serial clocking,
as follows:
DKVUUGEQPF  H_PBC  6%  Z UCORNKPI TCVG
where 6% is the 16-bit value programmed into the ASCI
Time Constant High and Low registers. If the ASCI multi-
plexed %-# pin is selected for the %-# function, it outputs
the clock before the final division by the sampling rate, as
follows:
H_{7E5‡†}  H_PBC  6% 
Find the 6% value for a particular serial bit rate as follows:
6%  H_PBC  Z DKVUUGEQPF Z UCORNKPI TCVG 
#5%+ 6KOG %QPUVCPV 4GIKUVGT  .QY #56%. +1 #FFTGUU #*
#5%+ 6KOG %QPUVCPV 4GIKUVGT  .QY #56%. +1 #FFTGUU %*
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#5%+ 6KOG %QPUVCPV 4GIKUVGT  *KIJ #56%* +1 #FFTGUU $*
#5%+ 6KOG %QPUVCPV 4GIKUVGT  *KIJ #56%* +1 #FFTGUU &*
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