Z8S18020VSG Datasheet, PDF (12/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

<5<.
'PJCPEGF < /KETQRTQEGUUQT
2+0 &'5%4+26+105 %QPVKPWGF
ways recognized at the end of an instruction, regardless of
the state of the interrupt-enable flip-flops. This signal forces
CPU execution to continue at location 0066H.
2*+ System Clock (Output). The output is used as a refer-
ence clock for the MPU and the external system. The fre-
quency of this output may be one-half, equal to, or twice
the crystal or input clock frequency.
4& Read (Output, active Low, 3-state). 4& indicates that
the CPU wants to read data from either memory or an I/O
device. The addressed I/O or memory device should use this
signal to gate data onto the CPU data bus.
4(5* Refresh (Output, active Low). Together with /4'3,
4(5* indicates that the current CPU machine cycle and the
contents of the address bus should be used for refresh of dy-
namic memories. The low-order 8 bits of the address bus
(# #) contain the refresh address. This signal is analogous
to the REF signal of the Z64180.
465 Request to Send 0 (Output, active Low); a program-
mable MODEM control signal for ASCI channel 0.
4:# 4:# Receive Data 0 and 1 (Input). These signals
are the receive data for the ASCI channels.
4:5 Clocked Serial Receive Data (Input). This line is the
receive data for the CSI/O channel. RXS is multiplexed with
the %65 signal for ASCI channel 1.
56 Status (Output). This signal is used with the / and
*#.6 output to decode the status of the CPU machine cycle.
See Table 3.
6CDNG  5VCVWU 5WOOCT[
56 *#.6 / 1RGTCVKQP
   %27 1RGTCVKQP UV 1REQFG (GVEJ
   %27 1RGTCVKQP PF 1REQFG CPF TF
1REQFG (GVEJ
   %27 1RGTCVKQP /% 'ZEGRV 1REQFG
(GVEJ
 :  &/# 1RGTCVKQP
   *#.6 /QFG
   5.''2 /QFG +PENWFKPI 5;56'/
5612 /QFG
Notes:
:  &Q PQV ECTG
/%  /CEJKPG %[ENG
ZiLOG
6'0& 6'0& Transfer End 0 and 1 (Outputs, active
Low). This output is asserted active during the most recent
94+6' cycle of a DMA operation. It is used to indicate the
end of the block transfer. 6'0& is multiplexed with %-#.
6'56 Test (Output, not in DIP version). This pin is for test
and should be left open.
6_IUT Timer Out (Output). 6_IUT is the output from PRT
channel 1. This line is multiplexed with # of the address
bus.
6:# 6:# Transmit Data 0 and 1 (Outputs). These sig-
nals are the transmitted data from the ASCI channels. Trans-
mitted data changes are with respect to the falling edge of
the transmit clock.
6:5 Clocked Serial Transmit Data (Output). This line is
the transmitted data from the CSI/O channel.
9#+6. Wait (Input, active Low). 9#+6 indicates to the
MPU that the addressed memory or I/O devices are not
ready for data transfer. This input is sampled on the falling
edge of 6 (and subsequent 9#+6 states). If the input is
sampled Low, then the additional 9#+6 states are inserted
until the 9#+6 input is sampled High, at which time exe-
cution continues.
94. 94+6' (Output, active Low, 3-state). 94 indicates that
the CPU data bus holds valid data to be stored at the ad-
dressed I/O or memory location.
:6#. Crystal Oscillator Connection (Input). This pin
should be left open if an external clock is used instead of a
crystal. The oscillator input is not a TTL level (see DC Char-
acteristics).
Several pins are used for different conditions, depending on
the circumstance.

24'.+/+0#4;
&5</2