Z8S18020VSG Datasheet, PDF (54/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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The DMA Destination Address Register Channel 0
specifies the physical destination address for channel 0
transfers. The register contains 20 bits and can specify up
to 1024-KB memory addresses or up to 64-KB I/O
addresses. Channel 0 destination can be memory, I/O, or
memory mapped I/O. For I/O, the /5 bits of this register
identify the Request Handshake signal for channel 0.
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If the DMA destination is in I/O space, bits   of this reg-
ister select the DMA request signal for DMA0, as follows:
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