Z8S18020VSG Datasheet, PDF (61/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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The DMA/WAIT Control Register (&%06.) controls the
insertion of wait states into DMAC (and CPU) accesses of
memory or I/O. Also, the register defines the Request signal
for each channel as level or edge sense. &%06. also sets
the DMA transfer mode for channel 1, which is limited to
memory to/from I/O transfers.
$KV 







/9+ /9+ +9+
49 49 49
+9+ &/5 &/5 &+/ &+/
49 49 49 49 49
(KIWTG  &/#9#+6 %QPVTQN 4GIKUVGT &%06. +1 #FFTGUU  *
/9+ /9+ /GOQT[ 9CKV +PUGTVKQP $KVU   T h i s
bit specifies the number of wait states introduced into CPU
or DMAC memory access cycles. /9+ and /9+ are set
to 1 during 4'5'6.
&/5K


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/9+




/9+




9CKV 5VCVG




+9+ +9+ +1 9CKV +PUGTVKQP $KVU   This bit speci-
fies the number of wait states introduced into CPU or DMAC
I/O access cycles. +9+ and +9+ are set to 1 during 4'5'6.
+9+




+9+




9CKV 5VCVG




0QVG These wait states are added to the 3-clock I/O cycle that
is used to access the on-chip I/O registers. It is equally
valid to regard these as 0 to 3 wait states added to a 4-
clock external I/O cycle.
&/5 &/5 &/# 4GSWGUV 5GPUG $KVU   & / 5 
and &/5 specify the DMA request sense for channel 0 and
channel 1 respectively. When reset to 0, the input is level
sense. When set to 1, the input is edge sense. &/5 and
&/5 are cleared to 0 during 4'5'6.
Typically, for an input/source device, the associated &/5
bit should be programmed as 0 for level sense. The device
takes a relatively long time to update its Request signal after
the DMA channel reads data (in the first of the two machine
cycles involved in transferring a byte).
An output/destination device takes much less time to update
its Request signal after the DMA channel starts a 94+6'
operation to it (the second machine cycle of the two cycles
involved in transferring a byte). With zero-wait state I/O cy-
cles, a device cannot update its request signal in the required
time, so edge sensing must be used.
A one-wait-state I/O cycle also does not provide sufficient
time for updating, so edge sensing is again required.
&+/ &+/ &/# %JCPPGN  +1 CPF /GOQT[ /QFG
$KVU   Specifies the source/destination and address
modifier for channel 1 memory to/from I/O transfer modes.
&+/ and &+/ are cleared to 0 during 4'5'6.
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