Z8S18020VSG Datasheet, PDF (24/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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ing the bus to an external Master during 56#0&$; mode,
when the $4':6 bit in the CPU Control Register (%%4)
is 1.
As described previously for 5.''2 and +&.' modes, when
the MPU leaves 56#0&$; mode due to 0/+ Low or an en-
abled +06–+06 Low when the +'(, flag is 1 due to an
IE instruction, it starts by performing the interrupt with the
return address being that of the instruction following the
5.2 instruction. If the Z8S180/Z8L180 leaves 56#0&$;
mode due to an external interrupt request that's enabled in
the +0664#2 Control Register, but the +'(, bit is 0 due to
a &+ instruction, the processor restarts by executing the in-
struction(s) following the 5.2 instruction. If +06, or +06
or +06 goes inactive before the end of the clock stabiliza-
tion delay, the Z8S180/Z8L180 stays in 56#0&$; mode.
Figure 17 indicates the timing for leaving 56#0&$; mode
due to an interrupt request.
0QVG The Z8S180/Z8L180 takes either 64 or 2¹⁷ (131,072)
clocks to restart, depending on the CCR3 bit.
56#0&$; /QFG
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While the Z8S180/Z8L180 is in 56#0&$; mode, it grants
the bus to an external Master if the $4':6 bit (%%4) is 1.
Figure 18 indicates the timing of this sequence. The device
takes 64 or 2¹⁷ (131,072) clock cycles to grant the bus de-
pending on the CCR3 bit. The latter (not the 37+%- 4'
%18'4;) case may be prohibitive for many demand-driven
external Masters. If so, 37+%- 4'%18'4; or +&.' mode
can be used.

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