Z8S18020VSG Datasheet, PDF (58/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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The DMA Status Register (&56#6) is used to enable and
disable DMA transfer and DMA termination interrupts.
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/PGOQPKE &56#6
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&56#6 also indicates DMA transfer status, Completed or
In Progress.
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&' &' &9' &9' &+' &+'
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&' &/# 'PCDNG %JCPPGN  $KV  When &'  1
and &/'  1, channel 1 DMA is enabled. When a DMA
transfer terminates ($%4  ), &' is reset to 0 by the
DMAC. When &'  0 and the DMA interrupt is enabled
(&+'  1), a DMA interrupt request is made to the CPU.
To perform a software 94+6' to &', &9' should be
written with a 0 during the same register 94+6' access.
Writing &' to 0 disables channel 1 DMA, but DMA is re-
startable. Writing &' to 1 enables channel 1 DMA and
automatically sets DMA Main Enable (&/') to 1. &' is
cleared to 0 during 4'5'6.
&' &/# 'PCDNG %JCPPGN  $KV  When &'  1
and &/'  1, channel 0 DMA is enabled. When a DMA
transfer terminates ($%4  ), &' is reset to 0 by the
DMAC. When &'  0 and the DMA interrupt is enabled
(&+'  1), a DMA interrupt request is made to the CPU.
To perform a software 94+6' to &', &9' should be
written with 0 during the same register 94+6' access. Writ-
ing &' to 0 disables channel 0 DMA. Writing &' to 1
enables channel 0 DMA and automatically sets DMA Main
Enable (&/') to 1. &' is cleared to 0 during 4'5'6.
&9' &' $KV 9TKVG 'PCDNG $KV  When performing
any software 94+6' to &', this bit should be written with
0 during the same access. &9' always reads as .
&9' &' $KV 9TKVG 'PCDNG $KV  When performing
any software 94+6' to &', this bit should be written with
0 during the same access. &9' always reads as .
&+' &/# +PVGTTWRV 'PCDNG %JCPPGN  $KV  W h e n
&+' is set to 1, the termination channel 1 DMA transfer
(indicated when &'  0) causes a CPU interrupt request
to be generated. When &+'  0, the channel 0 DMA ter-
mination interrupt is disabled. &+' is cleared to 0 during
4'5'6.
&+' &/# +PVGTTWRV 'PCDNG %JCPPGN  $KV  W h e n
&+' is set to 1, the termination channel 0 of DMA transfer
(indicated when &'  ) causes a CPU interrupt request
to be generated. When &+'  0, the channel 0 DMA ter-
mination interrupt is disabled. &+' is cleared to 0 during
4'5'6.
&/' &/# /CKP 'PCDNG $KV  A DMA operation is
only enabled when its &' bit (&' for channel 0, &' for
channel 1) and the &/' bit is set to .
When 0/+ occurs, &/' is reset to 0, thus disabling DMA
activity during the 0/+ interrupt service routine. To restart
DMA, &' and/or &' should be written with a 1 (even
if the contents are already ). This condition automatically
sets &/' to 1, allowing DMA operations to continue.
0QVG &/' cannot be directly written. The bit is cleared to 0
by 0/+ or indirectly set to 1 by setting &' and/or &'
to 1. &/' is cleared to 0 during 4'5'6.

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