Z8S18020VSG Datasheet, PDF (26/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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The following standard test conditions apply to DC Char-
acteristics, unless otherwise noted. All voltages are refer-
enced to V_SS (0V). Positive current flows into the refer-
enced pin.
All AC parameters assume a load capacitance of 100 pF.
Add a 10-ns delay for each 50-pF increase in load up to a
maximum of 200 pF for the data bus and 100 pF for the ad-
dress and control lines. AC timing measurements are ref-
erenced to V_OL MAX or V_OL MIN as indicated in Figures 20
through 30 (except for %.1%-, which is referenced to the
10% and 90% points). Ordering Information lists temper-
ature ranges and product numbers. Find package drawings
in Package Information.
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exceeded. Normal operation should be under recom-
mended operating conditions. If these conditions are ex-
ceeded, it could affect reliability.

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