Z8S18020VSG Datasheet, PDF (43/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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#5%+ %QPVTQN 4GIKUVGT $  %06.$ +1 #FFTGUU  *
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/2$6 /WNVKRTQEGUUQT $KV 6TCPUOKV $KV  When multi-
processor communication format is selected (/2 bit = ),
/2$6 is used to specify the /2$ data bit for transmission.
If /2$6  1, then /2$   is transmitted. If /2$6 
0, then /2$  0 is transmitted. The /2$6 state is unde-
fined during and after 4'5'6.
/2 /WNVKRTQEGUUQT /QFG $KV  When /2 is set to 1,
the data format is configured for multiprocessor mode based
on /1& (number of data bits) and /1& (number of stop
bits) in %06.#. The format is as follows:
5VCTV DKV  QT  FCVC DKVU /2$ DKV  QT  UVQR DKVU
Multiprocessor (/2  ) format offers no provision for
parity. If /2  0, the data format is based on /1&,
/1&, /1&, and may include parity. The /2 bit is
cleared to 0 during 4'5'6.
%6525 %NGCT VQ 5GPF2TGUECNG $KV  W h e n r e a d ,
%6525 reflects the state of the external %65 input. If the
%65 input pin is High, %6525 is read as 1.
0QVG When the %65 input pin is High, the 6&4' bit is inhib-
ited (that is, held at ).
For channel 1, the %65 input is multiplexed with 4:5 pin
(Clocked Serial Receive Data). Thus, %6525 is only valid
when read if the channel 1 %65' bit = 1 and the %65
input pin function is selected. The 4'#& data of %6525
is not affected by 4'5'6.
If the 55  bits in this register are not , and the $4)
mode bit in the #5':6 register is 0, then writing to this bit
sets the prescale (PS) control. Under those circumstances,
a 0 indicates a divide-by-10 prescale function while a 1
indicates divide-by-30. The bit resets to 0.
2'1 2CTKV[ 'XGP 1FF $KV   2'1 selects oven or odd
parity. 2'1 does not affect the enabling/disabling of parity
(/1& bit of %06.#). If 2'1 is cleared to 0, even parity
is selected. If 2'1 is set to 1, odd parity is selected. 2'1 is
cleared to 0 during 4'5'6.
&4 &KXKFG 4CVKQ $KV  If the : bit in the #5':6 reg-
ister is 0, this bit specifies the divider used to obtain baud
rate from the data sampling clock. If &4 is reset to 0, divide-
by-16 is used, while if &4 is set to 1, divide-by-64 is used.
&4 is cleared to 0 during 4'5'6.
55 5QWTEG5RGGF 5GNGEV  $KVU   F i r s t ,
if these bits are , as they are after a 4'5'6, the %-#
pin is used as a clock input, and is divided by 1, 16, or 64
depending on the &4 bit and the : bit in the #5':6 reg-
ister.
If these bits are not  and the $4) mode bit is #5':6
is 0, then these bits specify a power-of-two divider for the
2*+ clock as indicated in Table 10.
Setting or leaving these bits as  makes sense for a chan-
nel only when its %-# pin is selected for the %-# function.
%-#1%-5 offers the %-#1 function when bit 4 of the Sys-
tem Configuration Register is 0. &%&/%-# offers the
%-# function when bit 0 of the Interrupt Edge register is 1.
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