Z8S18020VSG Datasheet, PDF (40/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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Transmit Shift Register (654) receives data from the ASCI
Transmit Data Register (6&4), the data is shifted out to the
6:# pin. When transmission is completed, the next byte (if
available) is automatically loaded from 6&4 into 654 and
the next transmission starts. If no data is available for trans-
mission, 654 idles by outputting a continuous High level.
This register is not program-accessible
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 * * Data written to the ASCI Transmit Data
Register is transferred to the 654 as soon as 654 is empty.
Data can be written while 654 is shifting out the previous
byte of data. Thus, the ASCI transmitter is double buffered.

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