Z8S18020VSG Datasheet, PDF (17/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
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12'4#6+10 /1&'5
< XGTUWU  %QORCVKDKNKV[ The Z8S180/Z8L180
is descended from two different “ancestor” processors,
ZiLOG’s original Z80 and the Hitachi 64180. The Operat-
ing Mode Control Register (OMCR), illustrated in Figure
8, can be programmed to select between certain Z80 and
64180 differences.
& & &
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+1% 49
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/' 49
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/' / 'PCDNG This bit controls the / output and is
set to a 1 during 4'5'6.
When /'  1, the / output is asserted Low during op-
code fetch cycles, Interrupt Acknowledge cycles, and the
first machine cycle of an 0/+ acknowledge.
On the Z8S180/Z8L180, this choice makes the processor
fetch a 4'6+ instruction one time. When fetching a 4'6+
from a zero-wait-state memory location, the processor uses
three clock bus cycles. These bus cycles are not fully Z80-
timing compatible.
When /'  0, the processor does not drive / Low dur-
ing the instruction fetch cycles. After fetching a 4'6+ in-
struction with normal timing, the processor goes back and
refetches the instruction using fully Z80-compatible cycles
that include driving / Low. This option may be required
by some external Z80 peripherals to properly decode the
4'6+ instruction. Figure 9 and Table 5 show the 4'6+ se-
quence when /' is 0.
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6_! 6_C 6_ 6
6_! 6_C
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&_ &_%
2%
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2% 
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2%
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