Z8S18020VSG Datasheet, PDF (23/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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56#0&$; /QFG 9KVJ QT 9KVJQWV 37+%- 4'%18'4;
Software can put the Z8S180/Z8L180 into this mode by set-
ting the +15612 bit (ICR5) to 1, CCR6 to 1, and executing
the 5.2 instruction. This mode stops the on-chip oscillator
and thus draws the least power of any mode, less than 10µA.
As with +&.' mode, the Z8S180/Z8L180 leaves 56#0&$;
mode in response to a Low on 4'5'6, on 0/+, or a Low
on +06–2 that is enabled by a 1 in the corresponding bit
in the INT/TRAP Control Register. This action grants the
bus to an external Master if the BREXT bit in the CPU Con-
trol Register (CCR5) is 1. The time required for all of these
operations is greatly increased by the necessity for restart-
ing the on-chip oscillator, and ensuring that it stabilizes to
square-wave operation.
When an external clock is connected to the EXTAL pin rath-
er than a crystal to the XTAL and EXTAL pins and the ex-
ternal clock runs continuously, there is little necessity to use
56#0&$; mode because no time is required to restart the
oscillator, and other modes restart faster. However, if ex-
ternal logic stops the clock during 56#0&$; mode (for ex-
ample, by decoding *#.6 Low and / High for several
clock cycles), then 56#0&$; mode can be useful to allow
the external clock source to stabilize after it is re-enabled.
When external logic drives 4'5'6 Low to bring the device
out of 56#0&$; mode, and a crystal is in use or an external
clock source is stopped, the external logic must hold 4'5'6
Low until the on-chip oscillator or external clock source is
restarted and stabilized.
The clock-stability requirements of the Z8S180/Z8L180 are
much less in the divide-by-two mode that is selected by a
4'5'6 sequence and controlled by the Clock Divide bit in
the CPU Control Register (CCR7). As a result, software per-
forms the following actions:
1. Sets CCR7 to 0 for divide-by-two mode before an 5.2
instruction and 56#0&$; mode.
2. Delays setting CCR7 back to 1 for divide-by-one
mode as long as possible to allow additional clock
stabilization time after a 4'5'6, interrupt, or in-line
RESTART after an 5.2 01 instruction.
If CCR6 is set to 1 before the 5.2 instruction places the
MPU in 56#0&$; mode, the value of the CCR3 bit deter-
mines the length of the delay before the oscillator restarts
and stabilizes when it leaves 56#0&$; mode due to an ex-
ternal interrupt request. When CCR3 is 0, the
Z8S180/Z8L180 waits 2¹⁷ (131,072) clock cycles. When
CCR3 is 1, it waits 64 clock cycles. This state is called
37+%- 4'%18'4; mode. The same delay applies to grant-
&5</2
24'.+/+0#4;