Z8S18020VSG Datasheet, PDF (41/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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Data can be written into and read from the ASCI Transmit
Data Register. If data is read from the ASCI Transmit Data
Register, the ASCI data transmit operation is not affected
by this 4'#& operation.
#5%+ 4GEGKXG 5JKHV 4GIKUVGT  454 This register
receives data shifted in on the 4:# pin. When full, data is
automatically transferred to the ASCI Receive Data Regis-
ter (4&4) if it is empty. If 454 is not empty when the next
incoming data byte is shifted in, an overrun error occurs.
This register is not program accessible.
#5%+ 4GEGKXG &CVC (+(1  4&4 +1 #FFTGUU 
* * The ASCI Receive Data Register is a read-only
register. When a complete incoming data byte is assembled
in 454, it is automatically transferred to the 4 character Re-
ceive Data First-In First-Out ((+(1) memory. The oldest
character in the (+(1 (if any) can be read from the Receive
Data Register (4&4). The next incoming data byte can be
shifted into 454 while the (+(1 is full. Thus, the ASCI re-
ceiver is well buffered.
#5%+ 56#675 (+(1
This four-entry (+(1 contains Parity Error, Framing Error,
Rx Overrun, and Break status bits associated with each char-
acter in the receive data (+(1. The status of the oldest char-
acter (if any) can be read from the ASCI status registers.
#5%+ %*#00'. %10641. 4')+56'4 #
$KV

/2'
49
#5%+ %QPVTQN 4GIKUVGT #  %06.# +1 #FFTGUU  *







/2$4
4'
6'
465 '(4
/1& /1& /1&
49
49
49
49
49
49
49
$KV

/2'
49
#5%+ %QPVTQN 4GIKUVGT #  %06.# +1 #FFTGUU  *







/2$4
4'
6' _{%-#& '(4}
/1& /1& /1&
49
49
49
49
49
49
49
(KIWTG  #5%+ %JCPPGN %QPVTQN 4GIKUVGT #
/2' /WNVK2TQEGUUQT /QFG 'PCDNG $KV  T h e A S C I
features a multiprocessor communication mode that utilizes
an extra data bit for selective communication when a num-
ber of processors share a common serial bus. Multiproces-
sor data format is selected when the /2 bit in %06.$ is set
to 1. If multiprocessor mode is not selected (/2 bit in
%06.$  ), /2' has no effect. If multiprocessor mode
is selected, /2' enables or disables the wake-up feature as
follows. If /$' is set to 1, only received bytes in which the
multiprocessor bit (/2$ )   can affect the 4&4( and error
flags. Effectively, other bytes (with /2$  ) are ignored
by the ASCI. If /2' is reset to 0, all bytes, regardless of
the state of the /2$ data bit, affect the 4'&4 and error flags.
/2' is cleared to 0 during 4'5'6.
4' 4GEGKXGT 'PCDNG $KV  When 4' is set to 1, the ASCI
transmitter is enabled. When 6' is reset to 0, the transmitter
is disables and any transmit operation in progress is inter-
rupted. However, the 6&4' flag is not reset and the previous
contents of 6&4' are held. 6' is cleared to 0 in +15612
mode during 4'5'6.
6' 6TCPUOKVVGT 'PCDNG $KV  When 6' is set to 1, the
ASCI receiver is enabled. When 6' is reset to 0, the trans-
mitter is disabled and any transmit operation in progress is
interrupted. However, the 6&4' flag is not reset and the pre-
&5</2
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