Z8S18020VSG Datasheet, PDF (66/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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//7 %1//10 $#5' 4')+56'4
The Common Base Register (%$4) specifies the base ad-
dress (on 4-KB boundaries) used to generate a 20-bit phys-
//7 %QOOQP $CUG 4GIKUVGT
/PGOQPKE %$4
#FFTGUU *
ical address for Common Area 1 accesses. All bits of %$4
are reset to 0 during 4'5'6.








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(KIWTG  //7 %QOOQP $CUG 4GIKUVGT %$4 +1 #FFTGUU  *
//7 $#0- $#5' 4')+56'4
The Bank Base Register ($$4) specifies the base address
(on 4-KB boundaries) used to generate a 20-bit physical ad-
//7 $CPM $CUG 4GIKUVGT
/PGOQPKE $$4
#FFTGUU *
dress for Bank Area accesses. All bits of $$4 are reset to
0 during 4'5'6.








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(KIWTG  //7 $CPM $CUG 4GIKUVGT $$4 +1 #FFTGUU  *
//7 %1//10$#0- #4'# 4')+56'4
The Common/Bank Area Register (%$#4) specifies bound-
aries within the Z8S180/Z8L180 64-KB logical address
//7 %QOOQP$CPM #TGC 4GIKUVGT
/PGOQPKE %$#4
#FFTGUU #*
space for up to three areas; Common Area), Bank Area and
Common Area 1.








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