Z8S18020VSG Datasheet, PDF (19/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
<5<.
'PJCPEGF < /KETQRTQEGUUQT
6_
6
2*+
6_W
6_!
+143
4&
94
(KIWTG  +1 4GCF CPF 9TKVG %[ENGU YKVJ +1%  
When +1% = 0, the timing of the +143 and 4& signals match
the timing of the Z80. The +143 and 4& signals go active
as a result of the rising edge of T2. (Figure 12.)
6_
6
2*+
6_W
6_!
+143
4&
94
(KIWTG  +1 4GCF CPF 9TKVG %[ENGU YKVJ +1%  
*#.6 CPF .QY2QYGT 1RGTCVKPI /QFGU T h e
Z8S180/Z8L180 can operate in seven modes with respect
to activity and power consumption:
Normal Operation
*#.6 Mode
+15612 Mode
5.''2 Mode
5;56'/ 5612 Mode
+&.' Mode
56#0&$; Mode (with or without 37+%- 4'%18
'4;)
0QTOCN 1RGTCVKQP In this state, the Z8S180/Z8L180 pro-
cessor is fetching and running a program. All enabled func-
tions and portions of the device are active, and the *#.6
pin is High.
*#.6 /QFG This mode is entered by the *#.6 instruc-
tion. Thereafter, the Z8S180/Z8L180 processor continually
fetches the following opcode but does not execute it and
drives the *#.6, 56 and / pins all Low. The oscillator
and 2*+ pin remain Active. Interrupts and bus granting to
external Masters, and DRAM refresh can occur, and all on-
chip I/O devices continue to operate including the DMA
channels.
&5</2
24'.+/+0#4;