Z8S18020VSG Datasheet, PDF (60/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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Table 16 indicates all DMA transfer mode combinations of
&/, &/, 5/, and 5/. Because I/O to/from I/O trans-
fers are not implemented, 12 combinations are available.
ZiLOG
6CDNG  6TCPUHGT /QFG %QODKPCVKQPU
&/
&/
5/
5/
































































0QVG * Includes memory mapped I/O.
6TCPUHGT /QFG
/GOQT[→/GOQT[
/GOQT[→/GOQT[
/GOQT[→/GOQT[
+1→/GOQT[
/GOQT[→/GOQT[
/GOQT[→/GOQT[
/GOQT[→/GOQT[
+1→/GOQT[
/GOQT[→/GOQT[
/GOQT[→/GOQT[
4GUGTXGF
4GUGTXGF
/GOQT[→+1
/GOQT[→+1
4GUGTXGF
4GUGTXGF
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5#4  &#4 
5#4  &#4 
5#4 HKZGF &#4 
5#4 HKZGF &#4 
5#4  &#4 
5#4  &#4 
5#4 HKZGF &#4 
5#4 HKZGF &#4 
5#4  &#4 HKZGF
5#4  &#4 HKZGF
5#4  &#4 HKZGF
5#4  &#4 HKZGF
//1& /GOQT[ /QFG %JCPPGN  $KV  When chan-
nel 0 is configured for memory to/from memory transfers
there is no Request Handshake signal to control the transfer
timing. Instead, two automatic transfer timing modes are se-
lectable: burst (//1&  ) and cycle steal (//1&  ).
For burst memory to/from memory transfers, the DMAC
takes control of the bus continuously until the DMA transfer
completes (as indicated by the byte count register = ). In
cycle steal mode, the CPU is provided a cycle for each DMA
byte transfer cycle until the transfer is completed.
For channel 0 DMA with I/O source or destination, the se-
lected Request signal times the transfer ignoring //1&.
//1& is cleared to 0 during 4'5'6.

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