Z8S18020VSG Datasheet, PDF (67/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
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%# %#%# $KVU   %# specifies the start (Low) ad-
dress (on 4-KB boundaries) for Common Area 1. This con-
dition also determines the most recent address of the Bank
Area. All bits of %# are set to 1 during 4'5'6.
$# $# $KVU   $# specifies the start (Low) address
(on 4-KB boundaries) for the Bank Area. This condition
also determines the most recent address of Common Area
0. All bits of $# are set to 1 during 4'5'6.
12'4#6+10 /1&' %10641. 4')+56'4
The Z8S180/Z8L180 is descended from two different an-
cestor processors, ZiLOG’s original Z80 and the Hitachi
64180. The Operating Mode Control Register (1/%4) can
be programmed to select between certain differences be-
tween the Z80 and the 64180.
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/PGOQPKE 1/%4
#FFTGUU '*
& & &
4GUGTXGF
+1% 49
/6' 9
/' 49
/' / 'PCDNG This bit controls the / output and is
set to a 1 during reset.
When /'  1, the / output is asserted Low during the
opcode fetch cycle, the +06 acknowledge cycle, and the
first machine cycle of the 0/+ acknowledge.
On the Z8S180/Z8L180, this choice makes the processor
fetch one 4'6+ instruction. When fetching a 4'6+ from zero-
wait-state memory, the processor uses three clock machine
cycles that are not fully Z80-timing-compatible.
When /'  0, the processor does not drive / Low dur-
ing instruction fetch cycles. After fetching one 4'6+ instruc-
tion with normal timing, the processor returns and refetches
the instruction using Z80-compatible cycles that drive /
Low. This timing compatibility may be required by external
Z80 peripherals to properly decode the 4'6+ instruction.
(KIWTG  1RGTCVKPI %QPVTQN 4GIKUVGT
1/%4 +1 #FFTGUU  '*
T₁ T₂ T₃ T₁ T₂ T₃ T_I T_I T_I T₁ T₂ T₃
2*+
T_I T₁ T₂ T₃ T_I
A₀–A₁₈ (A₁₉)
D₀–D₇
PC
EDH
PC+1
4DH
PC
EDH
PC+1
4DH
M1
MREQ
RD
ST
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24'.+/+0#4;