Z8S18020VSG Datasheet, PDF (18/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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/6' / 6GORQTCT[ 'PCDNG This bit controls the tem-
porary assertion of the / signal. It is always read back as
a 1 and is set to 1 during 4'5'6.
When /' is set to 0 to accommodate certain external Z80
peripheral(s), those same device(s) may require a pulse on
/ after programming certain of their registers to complete
the function being programmed.
For example, when a control word is written to the Z80 PIO
to enable interrupts, no enable actually takes place until the
PIO sees an active / signal. When /6' = 1, there is no
change in the operation of the / signal, and /' controls
its function. When /6' = 0, the / output is asserted dur-
ing the next opcode fetch cycle regardless of the state pro-
grammed into the /' bit. This condition is only momen-
tary (one time) and it is not necessary to preprogram a 1
to disable the function (see Figure 10).
6_
6
6_!
6_
6
6_!
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(KIWTG  / 6GORQTCT[ 'PCDNG 6KOKPI
+1% +1 %QORCVKDKNKV[ This bit controls the timing of the
+143 and 4& signals. The bit is set to 1 by 4'5'6.
When +1% = 1, the +143 and 4& signals function the same
as the Z64180 (Figure 11).

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