Z8S18020VSG Datasheet, PDF (22/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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While the Z8S180/Z8L180 is in +&.' mode, it grants the bus
to an external Master if the BREXT bit (CCR5) is 1. Figure
16 depicts the timing for this sequence.
After the external Master negates the Bus Request, the
Z8S180/Z8L180 disables the 2*+ clock and remains in +&.'
mode.
0QVG A response to a bus request takes 8 clock cycles longer
than in normal operation.

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