Z8S18020VSG Datasheet, PDF (38/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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'PJCPEGF < /KETQRTQEGUUQT
%27 %10641. 4')+56'4
%27 %QPVTQN 4GIKUVGT %%4 This register controls the
basic clock rate, certain aspects of Power-Down modes, and
output drive/low-noise options (Figure 31).
%27 %QPVTQN 4GIKUVGT %%4
& & & & & & & &
%NQEM &KXKFG
  :6#.
  :6#.
56#0&$;+&.' 'PCDNG
  0Q 56#0&$;
  +&.' #HVGT 5.''2
  56#0&$; #HVGT 5.''2
  56#0&$; #HVGT 5.''2
%[ENG 'ZKV
37+%- 4'%18'4;
$4':6
  +IPQTG $754'3
QP 56#0&$;+&.'
  56#0&$;+&.' 'ZKV
QP $754'3
.0#&&#6#
  5VCPFCTF &TKXG
   &TKXG QP
# # & &
.0%27%6.
  5VCPFCTF &TKXG
   &TKXG QP %27
%QPVTQN 5KIPCNU
.0+1
  5VCPFCTF &TKXG
   &TKXG QP
)TQWR  +1 5KIPCNU
.02*+
  5VCPFCTF &TKXG
   &TKXG QP
2*+ 2KP
(KIWTG  %27 %QPVTQN 4GIKUVGT %%4 #FFTGUU (*
ZiLOG
$KV  Clock Divide Select. If this bit is 0, as it is after a 4'
5'6, the Z8S180/Z8L180 divides the frequency on the
:6#. pin(s) by two to obtain its Master clock 2*+. If this
bit is programmed as 1, the part uses the :6#. frequency
as 2*+ without division.
If an external oscillator is used in divide-by-one mode, the
minimum pulse width requirement provided in the AC
Characteristics must be satisfied.
$KVU  CPF  56#0&$;/+&.' Control. When these bits
are both 0, a 5.2 instruction makes the Z8S180/Z8L180 en-
ter 5.''2 or 5;56'/ 5612 mode, depending on the
+15612 bit (ICR5).
When D6 is 0 and D3 is 1, setting the +15612 bit (ICR5)
and executing a 5.2 instruction puts the Z8S180/Z8L180
into +&.' mode in which the on-chip oscillator runs, but its
output is blocked from the rest of the part, including 2*+ out.
When D6 is 1 and D3 is 0, setting +15612 (ICR5) and
executing a 5.2 instruction puts the part into 56#0&$;
mode, in which the on-chip oscillator is stopped and the part
allows 2¹⁷ (128K) clock cycles for the oscillator to stabilize
when it restarts.
When D6 and D3 are both 1, setting +15612 (+%4) and
executing a 5.2 instruction puts the part into 37+%- 4'
%18'4; 56#0&$; mode, in which the on-chip oscillator
is stopped, and the part allows only 64 clock cycles for the
oscillator to stabilize when it restarts.
The latter section, *#.6 and .19 219'4 modes, de-
scribes the subject more fully.
$KV  $4':6 T h i s b i t c o n t r o l s t h e a b i l i t y o f t h e
Z8S180/Z8L180 to honor a bus request during 56#0&$;
mode. If this bit is set to 1 and the part is in 56#0&$;
mode, a $754'3 is honored after the clock stabilization
timer is timed out.
$KV  .02*+ This bit controls the drive capability on the
2*+ Clock output. If this bit is set to 1, the 2*+ Clock output
is reduced to 33 percent of its drive capability.

24'.+/+0#4;
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