Z8S18020VSG Datasheet, PDF (53/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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The DMA Source Address Register Channel 0 specifies the
physical source address for channel 0 transfers. The register
contains 20 bits and can specify up to 1024 KB memory ad-
dresses or up to 64-KB I/O addresses. Channel 0 source can
be memory, I/O, or memory mapped I/O. For I/O, bits
  of this register identify the Request Handshake sig-
nal.
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If the source is in I/O space, bits   of this register select
the DMA request signal for DMA0, as follows:
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