Z8S18020VSG Datasheet, PDF (62/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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'PJCPEGF < /KETQRTQEGUUQT
ZiLOG
+06'44726 8'%614 .19 4')+56'4
Bits   of the Interrupt Vector Low Register (+_F) are used
as bits   of the synthesized interrupt vector during inter-
rupts for the +06 and +06 pins and for the DMAs, ASCIs,
+PVGTTWRV 8GEVQT .QY 4GIKUVGT
/PGOQPKE +.
#FFTGUU *
$KV ^



+.  +.  +. 
49 49 49
PRTs, and CSI/O. These three bits are cleared to 0 during
4'5'6 (Figure 74).




2TQITCOOCDNG
+PVGTTWRV 5QWTEG &GRGPFGPV %QFG
(KIWTG  +PVGTTWRV 8GEVQT .QY 4GIKUVGT +. +1 #FFTGUU  *
+0664#2 %10641. 4')+56'4
This register is used in handling 64#2 interrupts and to en-
able or disable Maskable Interrupt Level  and the +06
and +06 pins.
+0664#2 %QPVTQN 4GIKUVGT
/PGOQPKEU +6%
#FFTGUU *
$KV ^{ }

64#2 7(1
49 4

+6' +6' +6'
49 49 49
64#2 $KV  This bit is set to 1 when an undefined op-
code is fetched. 64#2 can be reset under program control
by writing it with a ; however, 64#2 cannot be written with
1 under program control. 64#2 is reset to 0 during 4'5'6.
7(1 7PFGHKPGF (GVEJ 1DLGEV $KV  When a 64#2 in-
terrupt occurs, the contents of 7(1 allow the starting ad-
dress of the undefined instruction to be determined. This in-
terrupt is necessary because the 64#2 may occur on either
the second or third byte of the opcode. 7(1 allows the
stacked PC value to be correctly adjusted. If 7(1  0, the
first opcode should be interpreted as the stacked 2%. If
7(1  1, the first opcode address is stacked 2%. 7(1 is
Read-Only.
+6'   +PVGTTWRV 'PCDNG    $KVU   + 6 ' 
and +6' enable and disable the external interrupt inputs
+06 and +06, respectively. +6' enables and disables in-
terrupts from:
'5%%
• Bidirectional Centronics controller
%6%U
• External interrupt input +06
A 1 in a bit enables the corresponding interrupt level while
a 0 disables it. A 4'5'6 sets +6' to 1 and clears +6'
and +6' to 0.
64#2 +PVGTTWRV The Z8S180/Z8L180 generates a 64#2
sequence when an undefined opcode fetch occurs. This fea-
ture can be used to increase software reliability, implement
an extended instruction set, or both. 64#2 may occur during
opcode fetch cycles and also if an undefined opcode is
fetched during the interrupt acknowledge cycle for +06
when Mode  is used.
When a 64#2 sequence occurs, the Z8S180/Z8L180:
1. Sets the 64#2 bit in the Interrupt 64#2/Control (+6%)
register to 1.
2. Saves the current Program Counter (PC) value,
reflecting the location of the undefined opcode, on the
stack.
3. Resumes execution at logical address 0.
0QVG If logical address 0000H is mapped to physical address
00000H, the vector is the same as for 4'5'6. In this
case, testing the 64#2 bit in +6% reveals whether the re-
start at physical address 00000H was caused by 4'5'6
or 64#2.

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