Z8S18020VSG Datasheet, PDF (55/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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The DMA Byte Count Register Channel 0 specifies the
number of bytes to be transferred. This register contains 16
bits and may specify up to 64-KB transfers. When one byte
is transferred, the register is decremented by one. If P bytes
should be transferred, P must be stored before the DMA op-
eration.
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