Z8S18020VSG Datasheet, PDF (11/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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# #_ Address Bus (Output, 3-state). # # form a
20-bit address bus. The Address Bus provides the address
for memory data bus exchanges (up to 1 MB) and I/O data
bus exchanges (up to 64 KB). The address bus enters a
high–impedance state during reset and external bus ac-
knowledge cycles. Address line # is multiplexed with the
output of PRT channel 1 (6_IUT, selected as address output
on reset), and address line # is not available in DIP ver-
sions of the Z8S180.
$75#%-. Bus Acknowledge (Output, active Low).
$75#%- indicates that the requesting device, the MPU ad-
dress and data bus, and some control signals enter their high-
impedance state.
$754'3 Bus Request (Input, active Low). This input is
used by external devices (such as DMA controllers) to re-
quest access to the system bus. This request demands a high-
er priority than 0/+ and is always recognized at the end of
the current machine cycle. This signal stops the CPU from
executing further instructions, places addresses, data buses,
and other control signals into the high-impedance state.
%-# %-# Asynchronous Clock 0 and 1 (bidirection-
al). When in output mode, these pins are the transmit and
receive clock outputs from the ASCI baud rate generators.
When in input mode, these pins serve as the external clock
inputs for the ASCI baud rate generators. %-# is multi-
plexed with &4'3, and %-# is multiplexed with 6'0&.
%-5 Serial Clock (bidirectional). This line is the clock for
the CSI/O channel.
%65 %65. Clear to send 0 and 1 (Inputs, active Low).
These lines are modem control signals for the ASCI chan-
nels. %65 is multiplexed with 4:5.
& & Data Bus = (bidirectional, 3-state). & & con-
stitute an 8-bit bidirectional data bus, used for the transfer
of information to and from I/O and memory devices. The
data bus enters the high-impedance state during reset and
external bus acknowledge cycles.
&%&. Data Carrier Detect 0 (Input, active Low); a pro-
grammable modem control signal for ASCI channel 0.
&4'3 &4'3. DMA Request 0 and 1 (Input, active
Low). &4'3 is used to request a DMA transfer from one
of the on-chip DMA channels. The DMA channels monitor
these inputs to determine when an external device is ready
for a 4'#& or 94+6' operation. These inputs can be pro-
grammed to be either level or edge sensed. &4'3 is mul-
tiplexed with %-#.
' Enable Clock (Output). This pin functions as a synchro-
nous, machine-cycle clock output during bus transactions.
':6#. External Clock Crystal (Input). Crystal oscillator
connections. An external clock can be input to the
Z8S180/Z8L180 on this pin when a crystal is not used. This
input is Schmitt triggered.
*#.6. *#.6/5.''2 (Output, active Low). This output is
asserted after the CPU executes either the *#.6 or 5.''2
instruction and is waiting for either a nonmaskable or a
maskable interrupt before operation can resume. It is also
used with the / and 56 signals to decode the status of the
CPU machine cycle.
+06. Maskable Interrupt Request 0 (Input, active Low).
This signal is generated by external I/O devices. The CPU
honors these requests at the end of the current instruction
cycle as long as the 0/+ and $754'3 signals are inactive.
The CPU acknowledges this interrupt request with an in-
terrupt acknowledge cycle. During this cycle, both the /
and +143 signals become active.
+06 +06. Maskable Interrupt Request 1 and 2 (Inputs,
active Low). This signal is generated by external I/O de-
vices. The CPU honors these requests at the end of the cur-
rent instruction cycle as long as the 0/+, $754'3, and +06
signals are inactive. The CPU acknowledges these requests
with an interrupt acknowledge cycle. Unlike the acknowl-
edgment for +06, neither the / or +143 signals become
active during this cycle.
+143. I/O Request (Output, active Low, 3-state). +143 in-
dicates that the address bus contains a valid I/O address for
an +1 4'#& or +1 94+6' operation. +143 is also gener-
ated, along with /, during the acknowledgment of the
+06 input signal to indicate that an interrupt response vec-
tor can be place onto the data bus. This signal is analogous
to the +1' signal of the Z64180.
/. Machine Cycle 1 (Output, active Low). Together with
/4'3, / indicates that the current cycle is the opcode-
fetch cycle of instruction execution. Together with +143,
/ indicates that the current cycle is for interrupt acknowl-
edgment. It is also used with the *#.6 and 56 signal to de-
code the status of the CPU machine cycle. This signal is
analogous to the .+4 signal of the Z64180.
/4'3. Memory Request (Output, active Low, 3-state).
/4'3 indicates that the address bus holds a valid address
for a memory 4'#& or memory 94+6' operation. This sig-
nal is analogous to the /' signal of Z64180.
0/+. Nonmaskable Interrupt (Input, negative edge trig-
gered). 0/+ demands a higher priority than +06 and is al-
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