Z8S18020VSG Datasheet, PDF (47/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
<5<.
'PJCPEGF < /KETQRTQEGUUQT
never both set to 1 at the same time. 6' is cleared to 0
during 4'5'6 and +15612 mode.
55   5RGGF 5GNGEV    $KVU   55 , 55
and 55 select the CSI/O transmit/receive clock source and
speed. 55, 55 and 55 are all set to 1 during 4'5'6.
Table 11 indicates CSI/O Baud Rate Selection.
6KOGT &CVC 4GIKUVGT %JCPPGN *
/PGOQPKE 6/&4*
#FFTGUU &*
   
6CDNG  %5+1 $CWF 4CVG 5GNGEVKQP
55 55 55
























&KXKFG 4CVKQ
÷
÷
÷
÷
÷
÷
÷
'ZVGTPCN %NQEM +PRWV
.GUU 6JCP ÷
6KOGT &CVC
(KIWTG  6KOGT &CVC 4GIKUVGT %JCPPGN  *KIJ
6KOGT 4GNQCF 4GIKUVGT %JCPPGN  .QY
/PGOQPKE 4.&4.
#FFTGUU '*
   
After 4'5'6, the %-5 pin is configured as an external clock
input (55 55 55  ). Changing these values causes
%-5 to become an output pin and the selected clock is output
when transmit or receive operations are enabled.
%5+1 6TCPUOKV4GEGKXG &CVC 4GIKUVGT
/PGOQPKE 64&4
#FFTGUU $*
   
6KOGT 4GNQCF &CVC
(KIWTG  6KOGT 4GNQCF 4GIKUVGT .QY
6KOGT 4GNQCF 4GIKUVGT %JCPPGN  *KIJ
/PGOQPKE 4.&4*
#FFTGUU (*
   
%5+1 64 &CVC
(KIWTG  %5+1 6TCPUOKV4GEGKXG &CVC 4GIKUVGT
6KOGT &CVC 4GIKUVGT %JCPPGN  .QY
/PGOQPKE 6/&4.
#FFTGUU %*
   
6KOGT 4GNQCF &CVC
(KIWTG  6KOGT 4GNQCF 4GIKUVGT %JCPPGN  *KIJ
#5%+ 4GEGKXG &CVC
(KIWTG  6KOGT 4GIKUVGT %JCPPGN  .QY
&5</2
24'.+/+0#4;