Z8S18020VSG Datasheet, PDF (45/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
<5<.
'PJCPEGF < /KETQRTQEGUUQT
#5%+ requests an interrupt when &%& goes High. 4+' is
cleared to 0 by 4'5'6.
&%& &CVC %CTTKGT &GVGEV $KV  56#6 This bit is set
to 1 when the pin is High. It is cleared to 0 on the first
4'#& of 56#6 following the pin’s transition from High
to Low and during 4'5'6. When bit 6 of the #5':6 reg-
ister is 0 to select auto-enabling, and the pin is negated
(High), the receiver is reset and its operation is inhibited.
%65' %NGCT 6Q 5GPF $KV  56#6 Channel 1 fea-
tures an external %65 input, which is multiplexed with the
receive data pin 45: for the CSI/O. Setting this bit to 1
selects the %65 function; clearing the bit to 0 selects the
4:5 function.
6&4' 6TCPUOKV &CVC 4GIKUVGT 'ORV[ $KV  6 & 4 ' 
1 indicates that the 6&4 is empty and the next transmit data
byte is written to 6&4. After the byte is written to 6&4,
6&4' is cleared to 0 until the ASCI transfers the byte from
6&4 to the 654 and then 6&4' is again set to 1. 6&4' is
set to 1 in +15612 mode and during 4'5'6. On ASCI0,
if the %65 pin is auto-enabled in the #5':6 register and
the pin is High, 6&4' is reset to 0.
6+' 6TCPUOKV +PVGTTWRV 'PCDNG $KV  6+' should be set
to 1 to enable ASCI transmit interrupt requests. If 6+' 
1, an interrupt is requested when 6&4'  1. 6+' is cleared
to 0 during 4'5'6.
#5%+ 64#05/+6 &#6# 4')+56'45
Register addresses 06H and 07H hold the ASCI transmit
data for channel 0 and channel 1, respectively.
#5%+ 6TCPUOKV &CVC 4GIKUVGTU %JCPPGN 
/PGOQPKE 6&4
#FFTGUU *
     
#5%+ 6TCPUOKV
%JCPPGN 
(KIWTG  #5%+ 4GIKUVGT
#5%+ 6TCPUOKV &CVC 4GIKUVGTU %JCPPGN 
/PGOQPKE 6&4
#FFTGUU *
     
#5%+ 6TCPUOKV
%JCPPGN 
(KIWTG  #5%+ 4GIKUVGT
&5</2
24'.+/+0#4;