Z8S18020VSG Datasheet, PDF (21/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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This condition provides a technique for synchronization
with high-speed external events without incurring the la-
tency imposed by an interrupt-response sequence. Figure 14
depicts the timing for exiting 5.''2 mode due to an inter-
rupt request.
0QVG The Z8S180/Z8L180 takes about 1.5 clock ticks to re-
start.
5.2 PF 1REQFG
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6
2*+
6_!
6_
5.''2 /QFG
6
6_S
6_S
1REQFG (GVEJ QT +PVGTTWRV
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6_
6
6_!
+06K 0/+
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5.2 PF 1REQFG #FFTGUU
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(KIWTG  5.''2 6KOKPI
+15612 /QFG +15612 mode is entered by setting the
+15612 bit of the I/O Control Register (+%4) to 1. In this
case, on-chip I/O (ASCI, CSI/O, PRT) stops operating.
However, the CPU continues to operate. Recovery from
+15612 mode is performed by resetting the +15612 bit in
+%4 to 0.
5;56'/ 5612 /QFG 5;56'/ 5612 mode is the com-
bination of 5.''2 and +15612 modes. 5;56'/ 5612
mode is entered by setting the +15612 bit in +%4 to 1 fol-
lowed by execution of the 5.2 instruction. In this mode, on-
chip I/O and CPU stop operating, reducing power consump-
tion, but the 2*+ output continues to operate. Recovery from
5;56'/ 5612 mode is the same as recovery from 5.''2
mode except that internal I/O sources (disabled by +15612)
cannot generate a recovery interrupt.
+&.' /QFG Software puts the Z8S180/Z8L180 into this
mode by performing the following actions:
Set the +15612 bit (+%4) to 
Set %%4 to 
Set %%4 to 
Execute the 5.2 instruction
The oscillator keeps operating but its output is blocked to
all circuitry including the 2*+ pin. DRAM refresh and all
internal devices stop, but external interrupts can occur. Bus
granting to external Masters can occur if the $4'56 bit in
the CPU control Register (%%4) was set to 1 before +&.'
mode was entered.
The Z8S180/Z8L180 leaves +&.' mode in response to a
Low on 4'5'6, an external interrupt request on 0/+, or an
external interrupt request on +06, +06 or +06 that is en-
abled in the INT/TRAP Control Register. As previously de-
scribed for 5.''2 mode, when the Z8S180/Z8L180 leaves
+&.' mode due to an 0/+, or due to an enabled external in-
terrupt request when the +'( flag is 1 due to an '+ instruc-
tion, the device starts by performing the interrupt with the
return address of the instruction after the 5.2 instruction.
If an external interrupt enables the INT/TRAP control reg-
ister while the +'( bit is 0, Z8S180/Z8L180 leaves +&.'
mode; specifically, the processor restarts by executing the
instructions following the 5.2 instruction.
Figure 15 indicates the timing for exiting +&.' mode due
to an interrupt request.
0QVG The Z8S180/Z8L180 takes about 9.5 clocks to restart.
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