Z8S18020VSG Datasheet, PDF (42/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

<5<.
'PJCPEGF < /KETQRTQEGUUQT
ZiLOG
#5%+ %*#00'. %10641. 4')+56'4 # %QPVKPWGF
vious contents of 6&4' are held. 6' is cleared to 0 in
+15612 mode during 4'5'6.
465 4GSWGUV VQ 5GPF %JCPPGN  $KV  KP %06.#
1PN[ If bit 4 of the System Configuration Register is 0,
the 465/6:5 pin exhibits the 465 function. 465 allows
the ASCI to control (start/stop) another communication de-
vices transmission (for example, by connecting to that de-
vice’s %65 input). 465 is essentially a 1-bit output port,
having no side effects on other ASCI registers or flags.
/1&
 →0Q RCTKV[
 →2CTKV[ GPCDNGF
/1&
 → UVQR DKV
 → UVQR DKVU
Bit 4 in %06.# is used.
%-#&   %-#6'0& RKP  6'0&
The data formats available based on all combinations of
/1&, /1&, and /1& are indicated in Table 9.
%-#&  , %-#6'0& RKP  %-#
These bits are cleared to 0 on reset.
/2$4'(4 /WNVKRTQEGUUQT $KV 4GEGKXG'TTQT (NCI 4GUGV
$KV  When multiprocessor mode is enabled (/2 in
%06.$  ), /2$4, when read, contains the value of the
/2$ bit for the most recent receive operation. When written
to 0, the '(4 function is selected to reset all error flags
(1840, (', 2' and $4- in the #5':6 Register) to 0.
/2$4/'(4 is undefined during 4'5'6.
/1&   #5%+ &CVC (QTOCV /QFG  DKVU  
These bits program the ASCI data format as follows.
/1&
 → DKV FCVC
6CDNG  &CVC (QTOCVU
/1& /1& /1& &CVC (QTOCV


 5VCTV  DKV FCVC  UVQR


 5VCTV  DKV FCVC  UVQR


 5VCTV  DKV FCVC RCTKV[
 UVQR


 5VCTV  DKV FCVC RCTKV[
 UVQR


 5VCTV  DKV FCVC  UVQR


 5VCTV  DKV FCVC  UVQR


 5VCTV  DKV FCVC RCTKV[
 UVQR


 5VCTV  DKV FCVC RCTKV[
 UVQR
 → DKV FCVC

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