Z8S18020VSG Datasheet, PDF (48/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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6+/'4 %10641. 4')+56'4
The Timer Control Register (6%4) monitors both channels
(246 246) 6/&4 status. It also controls the enabling
and disabling of down-counting and interrupts, and controls
the output pin #6_IUT for 246.
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6+(
4
6+(
4
6+'
49
6+'
49
61%
49
61%
49
6&'
49
6&'
49
(KIWTG  6KOGT %QPVTQN 4GIKUVGT 6%4 +1 #FFTGUU  *
6+( 6KOGT +PVGTTWRV (NCI  $KV   When 6/&4 dec-
rements to 0, 6+( is set to 1. This condition generates an
interrupt request if enabled by 6+'  1. 6+( is reset to 0
when 6%4 is read and the higher or lower byte of 6/&4
is read. During 4'5'6, 6+( is cleared to 0.
6+( 6KOGT +PVGTTWRV (NCI  $KV  When 6/&4 dec-
rements to 0, 6+( is set to 1. This condition generates an
interrupt request if enabled by 6+'  1. 6+( is reset to 0
when 6%4 is read and the higher or lower byte of 6/&4
is read. During 4'5'6, 6+( is cleared to 0.
6+' 6KOGT +PVGTTWRV 'PCDNG  $KV  When 6+' is set
to 1, 6+(  1 generates a CPU interrupt request. When
6+' is reset to 0, the interrupt request is inhibited. During
4'5'6, 6+' is cleared to 0.
61%  6KOGT 1WVRWV %QPVTQN $KVU   6 1 %  a n d
61% control the output of 246 using the multiplexed
#6_IUT pin as indicated in Table 12. During 4'5'6,
61% and 61% are cleared to 0. If bit 3 of the +#4$ reg-
ister is 1, the 6_IUT function is selected. By programming
61% and 61%, the #6_IUT pin can be forced High,
Low, or toggled when 6/&4 decrements to 0.
6CDNG  6KOGT 1WVRWV %QPVTQN
61% 61%








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6JG #6_IUT RKP KU PQV
CHHGEVGF D[ VJG 246
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6&'  6KOGT &QYP %QWPV 'PCDNG $KVU   6 & ' 
and 6&' enable and disable down-counting for 6/&4
and 6/&4, respectively. When 6&'P (P  ,) is set to
1, down-counting is stopped and 6/&4P is freely read or
written. 6&' and 6&' are cleared to 0 during 4'5'6 and
6/&4P does not decrement until 6&'P is set to .

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