Z8S18020VSG Datasheet, PDF (59/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
<5<.
'PJCPEGF < /KETQRTQEGUUQT
&/# /1&' 4')+56'4
The DMA Mode Register (&/1&') is used to set the ad-
dressing and transfer mode for channel 0.
&/# /QFG 4GIKUVGT
/PGOQPKE &/1&'
#FFTGUU *
$KV 







&/ &/ 5/ 5/ //1&
49 49 49 49 49
(KIWTG  &/# /QFG 4GIKUVGT &/1&' +1 #FFTGUU  *
&/ &/ &GUVKPCVKQP /QFG %JCPPGN  $KVU  This
mode specifies whether the destination for channel 0 transfers
is memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred. &/ and
&/ are cleared to 0 during 4'5'6.
6CDNG  %JCPPGN  &GUVKPCVKQP
&/




&/




/GOQT[ +1
/GOQT[
/GOQT[
/GOQT[
+1
/GOQT[
+PETGOGPV&GETGOGPV


HKZGF
HKZGF
5/ 5/ 5QWTEG /QFG %JCPPGN  $KVU    T h i s
mode specifies whether the source for channel 0 transfers
is memory or I/O, and whether the address should be incre-
mented or decremented for each byte transferred.
6CDNG  %JCPPGN  5QWTEG
5/




5/




/GOQT[ +1
/GOQT[
/GOQT[
/GOQT[
+1
/GOQT[
+PETGOGPV&GETGOGPV


HKZGF
HKZGF
&5</2
24'.+/+0#4;