Z8S18020VSG Datasheet, PDF (44/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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#5%+ 56#675 4')+56'4 
Each ASCI channel status register (56#6) allows inter-
rogation of ASCI communication, error and modem control
signal status, and the enabling or disabling of ASCI inter-
rupts.
#5%+ 5VCVWU 4GIKUVGT  56#6 +1 #FFTGUU  *
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4&4( 1840 2'
4
4
4
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4' &%& 6&4' 6+'
4
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4
4
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#5%+ 5VCVWU 4GIKUVGT  56#6 +1 #FFTGUU  *
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4&4( 1840 2'
4
4
4
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4' _%65' 6&4' 6+'
4
49 49 4
49
(KIWTG  #5%+ 5VCVWU 4GIKUVGTU
4&4( 4GEGKXG &CVC 4GIKUVGT (WNN $KV  4&4( is set to
1 when an incoming data byte is loaded into an empty 4Z
(+(1. If a framing or parity error occurs, 4&4( is still set
and the receive data (which generated the error) is still load-
ed into the (+(1. 4&4( is cleared to 0 by reading 4&4 and
most recently received character in the (+(1 from +15612
mode, during 4'5'6 and for #5%+ if the &%& input is
auto-enabled and is negated (High).
1840 1XGTTWP 'TTQT $KV  An overrun condition oc-
curs if the receiver finishes assembling a character but the
4Z (+(1 is full so there is no room for the character. How-
ever, this status bit is not set until the most recent character
received before the overrun becomes the oldest byte in the
(+(1. This bit is cleared when software writes a 1 to the
'(4 bit in the %06.# register. The bit may also be cleared
by 4'5'6 in +15612 mode or #5%+ if the &%& pin is
auto enabled and is negated (High).
0QVG When an overrun occurs, the receiver does not place the
character in the shift register into the (+(1, nor any sub-
sequent characters, until the most recent good character
enters the top of the (+(1 so that 1840 is set. Software
then writes a 1 to '(4 to clear it.
2' 2CTKV[ 'TTQT $KV  A parity error is detected when
parity checking is enabled.When the /1& bit in the
%06.# register is 1, a character is assembled in which the
parity does not match the 2'1 bit in the %06.$ register.
However, this status bit is not set until or unless the error
character becomes the oldest one in the 4Z (+(1. 2' is
cleared when software writes a 1 to the '(4 bit in the
%064.# register. 2' is also cleared by 4'5'6 in +15612
mode, or on #5%+, if the &%& pin is auto-enabled and is
negated (High).
(' (TCOKPI 'TTQT $KV  A framing error is detected
when the stop bit of a character is sampled as 52#%'.
However, this status bit is not set until/unless the error char-
acter becomes the oldest one in the 4Z (+(1. (' is cleared
when software writes a 1 to the '(4 bit in the %06.# reg-
ister. (' is also cleared by 4'5'6 in +15612 mode, or on
#5%+, if the &%& pin is auto-enabled and is negated
(High).
4'+ 4GEGKXG +PVGTTWRV 'PCDNG $KV  4+' should be set to
1 to enable ASCI receive interrupt requests. When 4+' is
1, the Receiver requests an interrupt when a character is re-
ceived and 4&4( is set, but only if neither DMA channel
requires its request-routing field to be set to receive data
from this ASCI. That is, if 5/  are  and 5#4 
are , or &+/ is 1 and +#4  are , then ASCI1
does not request an interrupt for 4&4(. If 4+' is 1, either
ASCI requests an interrupt when 1840, 2' or (' is set, and

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