Z8S18020VSG Datasheet, PDF (49/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

ZiLOG
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#5%+ ':6'05+10 %10641. 4')+56'4 %*#00'.  #0& %*#00'. 
The ASCI Extension Control Registers (#5':6 and ASCIs in the Z8S180/Z8L180 family. All bits in this
#5':6) control functions that have been added to the register reset to 0.
#5%+ 'ZVGPUKQP %QPVTQN 4GIKUVGT  #5':6 +1 #FFTGUU  *
$KV 







4GUGTXGF
&%&
&KUCDNG
%65
&KUCDNG
:
$4)
/QFG
$TGCM
'PCDNG
$TGCM
5GPF
$TGCM
#5%+ 'ZVGPUKQP %QPVTQN 4GIKUVGT  #5':6 +1 #FFTGUU  *
$KV








4GUGTXGF 4GUGTXGF 4GUGTXGF
:
$4)
/QFG
$TGCM
'PCDNG
$TGCM
5GPF
$TGCM
(KIWTG  #5%+ 'ZVGPUKQP %QPVTQN 4GIKUVGTU %JCPPGNU  CPF 
&%& &KUCDNG $KV  #5%+ 1PN[ If this bit is 0, then
the &%& pin auto-enables the ASCI0 receiver, such that
when the pin is negated/High, the Receiver is held in a 4'
5'6 state. If this bit is 1, the state of the &%&-pin has no
effect on receiver operation. In either state of this bit, soft-
ware can read the state of the &%& pin in the 56#6 reg-
ister, and the receiver interrupts on a rising edge of &%&.
%65 &KUCDNG $KV  #5%+ 1PN[ If this bit is 0, then the
%65 pin auto-enables the #5%+1 transmitter, in that when
the pin is negated/High, the 6&4' bit in the 56#6 register
is forced to 0. If this bit is 1, the state of the %65 pin has
no effect on the transmitter. Regardless of the state of this
bit, software can read the state of the %65 pin the %06.$
register.
: $KV  If this bit is 1, the clock from the Baud Rate
Generator or %-# pin is taken as a 1X-bit clock (sometimes
called isochronous mode). In this mode, receive data on the
4:# pin must be synchronized to the clock on the %-# pin,
regardless of whether %-# is an input or an output. If this
bit is 0, the clock from the Baud Rate Generator or %-#
pin is divided by 16 or 64 per the &4 bit in the %06.$ reg-
ister, to obtain the actual bit rate. In this mode, receive data
on the 4:# pin is not required to be synchronized to a clock.
$4) /QFG $KV  If the 55  bits in the %06.$ register
are not , and this bit is 0, the ASCI Baud Rate Generator
divides 2*+ by 10 or 30, depending on the 25 bit in %06.$,
and factored by a power of two (selected by the 55  bits),
to obtain the clock that is presented to the transmitter and
receiver and output on the %-# pin. If 55  are not ,
and this bit is 1, the Baud Rate Generator divides 2*+ by
twice the sum of the 16-bit value (programmed into the
Time Constant registers) and 2. This mode is identical to
the operation of the baud rate generator in the '5%%.
$TGCM 'PCDNG $KV  If this bit is 1, the receiver detects
$4'#- conditions and report them in bit 1, and the trans-
mitter sends $4'#-s under the control of bit 0.
$TGCM &GVGEV $KV  The receiver sets this read-only bit to
1 when an all-zero character with a Framing Error becomes
the oldest character in the 4Z (+(1. The bit is cleared when
software writes a 0 to the '(4 bit in %06.# register, also
by 4'5'6, by +15612 mode, and for #5%+, if the &%&
pin is auto-enabled and is negated (High).
5GPF $TGCM $KV  If this bit and bit 2 are both 1, the trans-
mitter holds the 6:# pin Low to send a $4'#- condition.
The duration of the $4'#- is under software control (one
of the PRTs or CTCs can be used to time it). This bit resets
to 0, in which state 6:# carries the serial output of the trans-
mitter.
&5</2
24'.+/+0#4;