Z8S18020VSG Datasheet, PDF (52/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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ZiLOG
$KV  .QY 0QKUG %T[UVCN 1RVKQP Setting this bit to 1 en-
ables the low-noise option for the ':6#. and :6#. pins.
This option reduces the gain in addition to reducing the out-
put drive capability to 30% of its original drive capability.
The Low Noise Crystal Option is recommended in the use
of crystals for PCMCIA applications, where the crystal may
be driven too hard by the oscillator. Setting this bit to 0 is
selected for normal operation of the ':6#. and :6#. pins.
The default for this bit is 0.
0QVG Operating restrictions for device operation are listed be-
low. If a low-noise option is required, and normal device
operation is required, use the clock multiplier feature.
$KV  : %NQEM /WNVKRNKGT /QFG When this bit is set to 1,
the programmer can double the internal clock speed from
the speed of the external clock. This feature only operates
effectively with frequencies of 10–16 MHz (20–32 MHz in-
ternal). When this bit is set to 0, the Z8S180/Z8L180 device
operates in normal mode. At power-up, this feature is dis-
abled.
6CDNG  .QY 0QKUG 1RVKQP
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