Z8S18020VSG Datasheet, PDF (65/71 Pages) Zilog, Inc. – Two Chain-Linked DMA Channels

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The Refresh Control Register (4%4) specifies the interval
and length of refresh cycles, while enabling or disabling the
refresh function.
4'(' 4GHTGUJ 'PCDNG $KV  4'('  0 disables the re-
fresh controller, while 4'('  1 enables refresh cycle in-
sertion. 4'(' is set to 1 during 4'5'6.
4'(9 4GHTGUJ 9CKV $KV  4'(9  0 causes the re-
fresh cycle to be two clocks in duration. 4'(9  1 causes
the refresh cycle to be three clocks in duration by adding a
refresh wait cycle (649). 4'(9 is set to 1 during 4'5'6.
%;%  %[ENG +PVGTXCN $KV  % ; %  a n d % ; % 
specify the interval (in clock cycles) between refresh cycles.
When dynamic RAM requires 128 refresh cycles every 2
ms (or 256 cycles in every 4 ms), the required refresh in-
terval is less than or equal to 15.625 µs. Thus, the underlined
values indicate the best refresh interval depending on CPU
clock frequency. %;% and %;% are cleared to 0 during
4'5'6 (see Table 18).
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4GHTGUJ %QPVTQN CPF 4GUGV After 4'5'6, based on the
initialized value of 4%4, refresh cycles occur with an inter-
val of 10 clock cycles and be 3 clock cycles in duration.
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1. Refresh Cycle insertion is stopped when the CPU is in
the following states:
a. During 4'5'6
b. When the bus is released in response to $754'3
c. During 5.''2 mode
d. During 9#+6 states
2. Refresh cycles are suppressed when the bus is released
in response to $754'3. However, the refresh timer
continues to operate. The time at which the first
refresh cycle occurs after the Z8S180/Z8L180
reacquires the bus depends on the refresh timer. This
cycle offers no timing relationship with the bus
exchange.
3. Refresh cycles are suppressed during 5.''2 mode. If
a refresh cycle is requested during 5.''2 mode, the
refresh cycle request is internally latched (until
replaced with the next refresh request). The latched
refresh cycle is inserted at the end of the first machine
cycle after 5.''2 mode is exited. After this initial
cycle, the time at which the next refresh cycle occurs
depends on the refresh time and offers no relationship
with the exit from 5.''2 mode.
4. The refresh address is incremented by one for each
successful refresh cycle, not for each refresh. Thus,
independent of the number of missed refresh requests,
each refresh bus cycle uses a refresh address
incremented by one from that of the previous refresh
bus cycles.
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