DS540 Datasheet, PDF (7/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 1: Top Level Parameters (Cont’d)
Generic Parameter Name
Description
Allowable Values
Default Value VHDL Type
G54
C_SUBSYSTEM_ID
Subsystem ID
16 bit vector (valid only 0x0000
for Endpoint)
std_logic_vector
G55
C_SUBSYSTEM_VENDOR_ID Subsystem Vendor 16 bit vector (valid only 0x0000
ID
for Endpoint)
std_logic_vector
G56
C_PCIE_CAP_SLOT_
IMPLEMENTED
PCIE Capabilities
Register Slot
Implemented
1 = Downstream port is 1
connected to add-in card
slot
0 = Not add-in card slot
(valid only for Root
Complex)
Integer
G57
C_REF_CLK_FREQ
REFCLK input
0 = 100 Mhz
0
frequency
(for V5, S6, V6)
1 = 125 Mhz
(for S6)
2 = 250 Mhz
(for V6)
Integer
IPIF Parameters
G58
C_MPLB_DWIDTH
PLB Master Bus
Data width
Automatically computed Automatically
by platgen
computed by
platgen
std_logic_vector
G59
C_MPLB_AWIDTH
PLB Master Bus 32
Address width
32
std_logic_vector
G60
C_MPLB_SMALLEST_SLAVE The data width of 32/64/128
the smallest slave
that will be
accessing this IPIF
32
std_logic_vector
G61
C_MPLB_NATIVE_DWIDTH Selects the Master 32 (for spartan6),
64
IPIF data width
64 (for virtex5 or virtex6)
integer
G62
C_SPLB_DWIDTH
PLB Slave Bus Data Automatically computed Automatically
width
by platgen
computed by
platgen
std_logic_vector
G63
C_SPLB_AWIDTH
PLB Slave Bus
32
Address width
32
std_logic_vector
G64
C_SPLB_MID_WIDTH
PLB Master ID Bus 3
Width
log2(C_SPLB_ Integer
NUM_MASTER
S)
G65
C_SPLB_NUM_MASTERS
Number of masters 1-8
on the bus
1
Integer
G66
C_SPLB_SMALLEST_
MASTER
The data width of
the smallest master
that will be
accessing this IPIF
32/64/128
32
std_logic_vector
G67
C_SPLB_NATIVE_DWIDTH Selects the Slave 32 (for spartan6),
64
IPIF data width
64 (for virtex5 or virtex6)
integer
DS540 June 22, 2011
www.xilinx.com
7
Product Specification