DS540 Datasheet, PDF (1/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

DS540 June 22, 2011
LogiCORE IP PLBv46 RC/EP
Bridge for PCI Express (v4.07.a)
Product Specification
Introduction
This document defines the functional operation of the
PLBv46 Root Complex and Endpoint Bridge for PCI
Express^®, hereafter called PLBv46 Bridge. The PLBv46
Bridge is an interface between the Processor Local Bus
(PLB) and the PCI Express (PCIe^®) bus.
This document provides the definitions for all of the
functional modules, registers, and interfaces that need
to be implemented in the PLBv46 Bridge. This
document defines the hardware implementation and
software interfaces to the PLBv46 Bridge in a FPGA.
Features
• Configurable Root Complex or Endpoint
functionality for Virtex^®-6 FPGA
• Endpoint functionality for Virtex-5 and Spartan^®-6
FPGAs
• Supports PLB access to PCIe space
• Supports PCIe access to PLB space
• Translates PLB transactions to appropriate PCIe
Transaction Layer Packets (TLPs)
• Tracks and manages TLPs that require completion
processing
• Indicates error conditions detected by the PCIe
core through interrupts
• Supports up to six 32-bit or six 64-bit remote PLB
Base Address Register (BAR) regions mapped to
PCIe address space
• Address spaces are defined with a base address, an
upper address, space type (I/O or Memory) and an
address translation value
• I/O space with 32-bit address supported when the
Virtex-6 FPGA is configured as Root Complex
• Supports up to three 32-bit or 64-bit PCIe Base
Address Register (BAR) memory regions mapped
to PLB address space when configured as
Endpoint
LogiCORE IP Facts
Core Specifics
Supported Device
Family ⁽¹⁾
Virtex-6, Spartan-6, Virtex-5
Supported User
Interfaces
plbv46, pcie
Resources
See Table 19.
Provided with Core
Documentation
Product Specification
Design Files
VHDL
Example Design
Not Provided
Test Bench
VHDL
Constraints File
.ucf (user constraints file)
Simulation Model
Not Provided
Tested Design Tools
Design Entry Tools
Simulation
Synthesis Tools
ISE v13.2 software
Mentor Graphics ModelSim⁽²⁾
XST 13.2
Support
Provided by Xilinx, Inc.
1. For a complete listing of supported devices, see IDS Embedded
Edition Derivative Device Support for this core.
2. For the supported version of the tool, see the ISE Design Suite 13:
Release Notes Guide.
© Copyright 2010-2011. Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of
Xilinx in the United States and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property
of their respective owners.
DS540 June 22, 2011
www.xilinx.com
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Product Specification