DS540 Datasheet, PDF (25/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Enhanced Configuration Access Mechanism
The PLBv46 Bridge implements the PCI Express Enhanced Configuration Access Mechanism (ECAM) when
configured with Root Complex capability. This mechanism uses a memory-mapped address space, as defined by
the C_ECAM_BASEADDR and C_ECAM_HIGHADDR parameters. Read and write accesses to this address space
are mapped to PCI Express Configuration space as defined in Table 15. The PLB address is used to define the
various fields in the Configuration read and write request Packet headers. The PCIe Bus Number(s) supported by
the bridge as a Root Complex is defined by the size of the number of address bits n allocated to the Bus Number
field in the ECAM address space. For example: with n = 2, there are 2² = 4 possible PCIe Bus Numbers. The value
of n is implied by the ECAM range as defined by the C_ECAM_BASEADDR and C_ECAM_HIGHADDR
parameters.
The BME bit of the Bridge Control Register (BCR) must be enabled for ECAM access. ECAM memory space is to be
accessed only by single data beat transactions. If burst transactions are attempted, the behavior is not defined. It is
the responsibility of software to ensure that a configuration write has completed before attempting a configuration
read.
When an ECAM access is attempted to a bus number that is out of the bus_number and subordinate bus number set
by the platform specific code within the Type 1 Configuration Space Header, the bridge does not stop the generated
configuration request. In the case of a write request, the bridge sets an SUR interrupt if an UR status is received in
the completion. If no completion was received, the bridge sets an STO interrupt. For the read request case, see
Configuration Read Response in the Slave Side Abnormal Conditions section.
Table 15: Enhanced Configuration Address Mapping
PLB Address
PCI Express Configuration Space
[ 12 – n :11]
Bus Number 1 ≤ n ≤ 8
[12:16]
Device Number
[17:19]
Function Number
[20:23]
Extended Register Number
[24:29]
Register Number
[30:31]
Along with size of the access, used to generate Byte Enables
Platform Specific SW Requirements
As part of the root complex functionality and before the enumeration procedure for remote devices start, platform
specific SW must set type 1 configuration space registers, the Requester ID register, and the BME bit of the bridge
control register (BCR). This is "self-configuration" and is performed via the memory mapped range offset 0x2000-
0x3fff and the offset 0x34 PRIDR register. The BME bit must be set after the Requester ID register is set in order for
the Power Limit Message to contain the set Requester ID register value. As with the EP configuration, PCIe to PLB
transactions after enumeration must be enabled by bits in the BCR as well. The required order is as follows:
1. Self-configure via the management interface
2. Set the Requester ID register value
3. Set BCR
4. Enumerate via ECAM
DS540 June 22, 2011
www.xilinx.com
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Product Specification