DS540 Datasheet, PDF (22/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 11: Bridge Interrupt Register Bit Definitions (Cont’d)
Bit(s)
Name
Core
Access
Reset
Value
Description
13-16
Reserved
Bus Master Enable: Asserted when the BME bit is set in the Command
17
BME R/TOW
0b
register of the PCI configuration header to enable the Bridge to send memory
requests. As an EP, this typically happens when an external Root Complex
does enumeration. As an RC, this happens during self-configuration.
18-31
Reserved
Bridge Interrupt Enable Register (BIER, Offset 0x44)
The Bridge Interrupt Enable Register shown in Figure 7 is used to enable/disable (or mask) the Bridge status bits to
the Bridge Interrupt Register (offset 0x40).
X-Ref Target - Figure 7
Reserved
MSI
MUR MEP
SEP SBO LNKDN
Reserved
0 1 2 3 4 5 6 7 8 9 10 11 12 13
16 17 18
31
SUR MCA SUC SCT SCA NBE
Reserved BME
Figure 7: Bridge Interrupt Enable Register
DS540_07_122309
Table 12: Bridge Interrupt Enable Register
Bit(s)
Name
Core
Access
Reset Value
Description
0
Reserved
1
SUR
R/W
Slave Unsupported Request Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
2
MUR
R/W
Master Unsupported Request Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
3
MCA
R/W
Master Completion Abort Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
4
MEP
R/W
Master Error Poison Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
5
SUC
R/W
Slave Unexpected Completion Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
6
MSI
R/W
Message Signaled Interrupt Enable:
0
1- Enables Interrupt
0- Disables Interrupt
Implemented only when C_INCLUDE_RC=1
7
SCT
R/W
Slave Completion Timeout Enable:
0b
1- Enables Interrupt
0- Disables Interrupt
DS540 June 22, 2011
www.xilinx.com
22
Product Specification