DS540 Datasheet, PDF (6/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 1: Top Level Parameters (Cont’d)
Generic Parameter Name
Description
Allowable Values
G42
C_PCIBAR_AS
Configures PCIBAR
aperture width to be
32 bits wide or 64
bits wide
0 = Generates three 32-
bit PCIBAR address
apertures.
32-bit BAR example:
PCIBAR_0 is 32 bits
PCIBAR_1 is 32 bits
PCIBAR_2 is 32 bits
Default Value VHDL Type
1
Integer
1 = Generates three 64-
bit PCIBAR address
apertures.
64-bit BAR example:
PCIBAR_0 and
PCIBAR_1 concatenate
to comprise 64-bit
PCIBAR_0.
PCIBAR_2 and
PCIBAR_3 concatenate
to comprise 64-bit
PCIBAR_1.
G43
C_PCIBAR_LEN_0
G44
C_PCIBAR2IPIFBAR_0
G45
C_PCIBAR_LEN_1
G46
C_PCIBAR2IPIFBAR_1
G47
C_PCIBAR_LEN_2
G48
C_PCIBAR2IPIFBAR_2
G49
C_NO_OF_LANES
G50
C_DEVICE_ID
G51
C_VENDOR_ID
G52
C_CLASS_CODE
G53
C_REV_ID
PCIBAR_4 and
PCIBAR_5 concatenate
to comprise 64-bit
PCIBAR_2
Power of 2 in the 13-29
size of bytes of PCI
BAR_0 space
PLB BAR to which
PCI BAR_0 is
mapped
Valid PLB address
Power of 2 in the 13-29
size of bytes of PCI
BAR_1 space
PLB BAR to which
PCI BAR_1 is
mapped
Valid PLB address
Power of 2 in the 13-29
size of bytes of PCI
BAR_2 space
PLB BAR to which
PCI BAR_2 is
mapped
Valid PLB address
PCIe Core Configuration Parameters
Number of PCIe
Lanes
1 - V5, V6, S6
4, 8 - V5 only
Device ID
16 bit vector
Vendor ID
16 bit vector
Class Code
24 bit vector
Rev ID
8 bit vector
16
0x0000_0000
16
0x0000_0000
16
0x0000_0000
1
0x0000
0x0000
0x00_0000
0x00
Integer
std_logic_vector
Integer
std_logic_vector
Integer
std_logic_vector
Integer
std_logic_vector
std_logic_vector
std_logic_vector
std_logic_vector
DS540 June 22, 2011
www.xilinx.com
6
Product Specification