DS540 Datasheet, PDF (14/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Table 3: Top Level Interface Signals (Cont’d)
Signal Name
I/O
Description
M_request
O
Master bus request
M_RNW
O
Master read not write
M_size[0:3]
O
Master transfer size
M_type
O
Master transfer type
M_wrBurst
O
Master burst write transfer indicator
M_wrDBus[0:C_MPLB_DWIDTH -1]
O
Master write data bus
M_LockErr
O
Master lock error
M_TAttribute[0:15]
O
Master Attribute
M_UABus[0:31]
O
Master Upper Address Bus
PCIe Interface
REFCLK
I
PCIe Reference Clock
Bridge_Clk
O
125 MHz for Virtex-5 and Virtex-6 FPGAs
62.5 Mhz for Spartan-6 FPGAs
(Used for debug only)
MSI_Request
I
Initiates a MSI write request
RXP[C_NO_OF_LANES-1 : 0]
I
RX serial interface
RXN[C_NO_OF_LANES-1 : 0]
I
RX serial interface
TXP[C_NO_OF_LANES-1 : 0]
O
TX serial interface
TXN[C_NO_OF_LANES-1 :0]
O
TX serial interface
Test Bench Debug Interface
TB_Debug
O
bit 0 - indicates MRd TLP sent from bridge
bit 1 - indicates MWr TLP sent from bridge
bit 2 through 15 - reserved
1. SPLB_Clk and MPLB_Clk must be connected to the same clock source.
DS540 June 22, 2011
www.xilinx.com
14
Product Specification