DS540 Datasheet, PDF (41/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
NET "plbv46_pcie_0/*Bridge_Clk"
TNM_NET = "Bridge_Clk";
TIMESPEC "TS_PLB_PCIe" = FROM "SPLB_Clk" TO "Bridge_Clk" 8 ns datapathonly;
TIMESPEC "TS_PCIe_PLB" = FROM "Bridge_Clk" TO "SPLB_Clk" 10 ns datapathonly;
ModelSim Simulation Notes
When simulating with ModelSim, the vsim options -L XilinxCoreLib_ver, -L secureip and -L unisims_ver must be
set.
Timing
When building a system in Virtex-5 FPGA hardware, set the “-xe c” and “-ol high” switches for both MAP and PAR
so that the core meets timing.
Device Utilization and Performance Benchmarks
System Performance
To measure the performance (F_MAX) of the PLBv46 Endpoint Bridge core, it was added to the Virtex-5 FPGA system
shown in Figure 8.
Because the PLBv46 Bridge core is used with other design modules in the FPGA, the utilization and timing numbers
reported in this section are estimates only. When this core is combined with other design modules in the system, the
utilization of FPGA resources and timing of the core design varies from the results reported here.
X-Ref Target - Figure 8
XCL
XCL
MPMC
XPS CDMA XPS CDMA
Device Under
Test (DUT)
MicroBlaze
Processor
PLBV46
XPS BRAM
XPS INTC
XPS GPIO
XPS UART
Lite
MMDDMM
DS540_08_122309
Figure 8: Performance of the Virtex-5 FPGA System Using the PLBv46 Endpoint as the DUT
Subsequently, the target FPGA listed in Table 18 is filled with logic to drive the LUT and block RAM utilization to
approximately 70% and the I/O utilization to approximately 80%. Using the default tool options and the slowest
speed grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 18.
Table 18: XPS PLBv46 Endpoint Core System Performance
Target FPGA
V5LXT50 -1
Target F_MAX (MHz)
120
The target F_MAX is influenced by the exact system and is provided for guidance only. It is not a guaranteed value
across all systems.
DS540 June 22, 2011
www.xilinx.com
41
Product Specification