DS540 Datasheet, PDF (24/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
MSI Data Register (MDR, Offset 0x4C)
The MSI Data Register shown in Table 14 provides the data value that is contained in an MSI MemWr TLP when it
is received from the PCIe Bus. When the conditions are met for generating an MSI interrupt, as defined in the
preceding MSI Address Register description, the single dword (32-bit) payload contained in the MSI MemWr TLP
is written into this register.
Table 14: MSI Data Register Bit definitions
Bits
31-0
Name
MSI Data
Core
Access
R
Reset Value
0000_0000h
Description
MSI Data: The data from the last received MSI MemWr TLP.
Clock and Reset Interface
Clock Interface
Xilinx recommends using the 100 MHz differential clock from the host PCI Express connector edge and connecting
the differential inputs to a differential to single ended utility core. The output of the utility core needs to connect to
the REFCLK input of the Bridge. The C_REF_CLK_FREQ parameter must be set to 100 Mhz if this clock is used.
Reset Interface
The MPLB_Rst and SPLB_Rst must be asserted simultaneously and held for a minimum of 300 ns. When using the
EDK tools to build a system, the user is encouraged to connect the PERSTN pin of the host PCIe connector to the
aux_reset_in port of the Proc_Sys_Reset module. The bus_struct_reset output of the Proc_Sys_Reset
module must then be connected to the sys_rst input of the PLBv46 bus module. The assignment of the PLBv46 bus
module instance label to the plbv46_pcie BUS_INTERFACE_SPLB and BUS_INTERFACE_MPLB causes the
PLBv46 bus module plb_rst output to be connected to the MPLB_Rst and SPLB_Rst of the Bridge for proper
reset operation
Link Down and Hot Reset as Endpoint
When the Link goes down or when a Hot Reset is received the hard core is reset and the internal LinkUp output
from the hard core deasserts. When the PLBv46 Bridge detects the deassertion of LinkUp from the hard core the
Bridge discards any ingress/egress TLPs that were in transit and sets the LinkDown interrupt in the Bridge
Interrupt Register. The internal bridge registers which are not in the PCI configuration header space and bridge
state machines are not reset by the Hot Reset. All PLB requests to the PLBv46 Bridge are re-arbitrated when the link
is down
Generating Hot Reset as Root Complex
Hot Reset can be generated by a write of 1 to the Bridge Control register bit 6 within the Type 1 Configuration Space
Header via the management interface. Initiating the Hot Reset causes the link to go down and link train. This bit is
automatically cleared after the link is down. When the PLBv46 Bridge detects the deassertion of LinkUp from the
hard core the Bridge discards any ingress/egress TLPs that were in transit and sets the LinkDown interrupt in the
Bridge Interrupt Register. The PCIe hard core, internal bridge registers and bridge state machines are not reset by
the Hot Reset. Hot Resets do not go upstream, so a switch cannot send a Hot Reset to the bridge when it is
configured as a Root Complex. After a Hot Reset, initialization must start within 80 ms. Self configuration is not
needed since the bridge and PCIe hard core are not reset. All PLB requests to the PLBv46 Bridge are re-arbitrated
when the link is down.
DS540 June 22, 2011
www.xilinx.com
24
Product Specification