DS540 Datasheet, PDF (45/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)
Revision History
Date
8/28/08
9/10/08
4/24/09
6/24/09
9/16/09
12/2/09
4/19/10
9/21/10
12/14/10
06/22/11
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Revision
Initial Xilinx Release (v3.00a)
Updated version to v3.00b, EDK_11.1; updated margin system F_MAX requirements;
see change log for specific changes.
Replaced device families and tools with hyperlink.
Updated to v4.01a, EDK 11.2 release; added Virtex-6 and Spartan-6 support
(including lane support and respective parameters for same); see change log for
specific changes.
Updated to v4.02a for EDK 11.3 release; added Root Complex Capability for
Virtex 6
Created v4.03a for EDK 11.4 release; converted to current data sheet template.
Created v4.04a for EDK 12.1 release.
Created v4.05a for EDK 12.3 release.
Created v4.06.a for EDK 12.4 release.
Created v4.07.a for EDK 13.2 release.
Notice of Disclaimer
The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To
the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby
DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT
LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR
PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including
your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss
of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such
damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no
obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product
specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent.
Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at
http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to
you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe
performance; you assume sole risk and liability for use of Xilinx products in Critical Applications:
http://www.xilinx.com/warranty.htm#critapps.
DS540 June 22, 2011
www.xilinx.com
45
Product Specification