DS540 Datasheet, PDF(27/45 Page) Xilinx, Inc – Supports PCIe access to PLB space

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DS540 Datasheet, PDF (27/45 Pages) Xilinx, Inc – Supports PCIe access to PLB space

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LogiCORE IP PLBv46 RC/EP Bridge for PCI Express (v4.07.a)

Example 2

This example shows the generic settings to set up 3 independent 64-bit IPIF BARs and address translation of PLB

addresses to a remote PCIe address space. This setting of IPIF BARs does not depend on the PCIe BARs within the

Bridge.

In this example, where C_IPIFBAR_NUM=3, the following assignments for each range are made:

C_IPIFBAR_AS_0=1

C_IPIFBAR_0=0x12340000

C_IPIF_HIGHADDR_0=0x1234FFFF

C_IPIFBAR2PCIBAR_0=0x500000005671XXXX (Bits 48-63 are donât cares)

C_IPIFBAR_AS_1=1

C_IPIFBAR_1=0xABCDE000

C_IPIF_HIGHADDR_1=0xABCDFFFF

C_IPIFBAR2PCIBAR_1=0x60000000FEDC0XXX (Bits 51-63 are donât cares)

C_IPIFBAR_AS_2=1

C_IPIFBAR_2=0xFE000000

C_IPIF_HIGHADDR_2=0xFFFFFFFF

C_IPIFBAR2PCIBAR_2=0x7000000040XXXXXX (Bits 39-63 are donât cares)

Accessing the Bridge IPIFBAR_0 with address 0x12340ABC on the PLB bus yields 0x5000000056710ABC on the

PCIe bus.

Accessing the Bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus yields 0x60000000FEDC1123 on the

PCIe bus.

Accessing the Bridge IPIFBAR_2 with address 0xFFFEDCBA on the PLB bus yields 0x7000000041FEDCBA on the

PCIe bus.

Example 3

This example shows the generic settings to set up 2 independent PCIe BARs and address translation of PCIe

addresses to a remote PLB address space. This setting of PCIe BARs does not depend on the IPIF BARs within the

Bridge. The C_PCIBAR_LEN_n parameter has a maximum value of 29, thus the maximum allowable address space

is 229 = 512M per BAR.

In this example, where C_PCIBAR_NUM=2, the following range assignments are made:

BAR 0 is set to 0x20000000ABCDE800 by the Root Complex

C_PCIBAR_LEN_0=11

C_PCIBAR2IPIFBAR_0=0x123450XX (Bits 21-31 are donât cares)

BAR 1 is set to 0xA000000012000000 by Root Complex

C_PCIBAR_LEN_1=25

C_PCIBAR2IPIFBAR_1=0xFEXXXXXX (Bits 7-31 are donât cares)

Accessing the Bridge PCIBAR_0 with address 0x20000000ABCDEFF4 on the PCIe bus yields 0x123457F4 on the

PLB bus.

Accessing Bridge PCIBAR_1 with address 0xA00000001235FEDC on the PCIe bus yields 0xFE35FEDC on the PLB

bus.

DS540 June 22, 2011

www.xilinx.com

27

Product Specification

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